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When the devices are scaled to decanano dimensions the discreteness of charge and matter introduces significant 'intrinsic' parameter fluctuations. Atomic level 3D process and device modelling on statistical scale is required to understand the effects, the scale of the fluctuations and to design fluctuation resistant devices.
Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.
This paper describes two linked technology development projects to support Space Shuttle ground operations personnel, both during mission preparation analysis and related analyses in missions. The Space Propulsion Robust Analysis Tool (SPRAT) will provide intelligent support and automation for mission analysis setup, interpretation, reporting and documentation. SPRAT models the actions taken by flight support personnel during mission preparation and uses this model to generate an action plan. CONFIG will provide intelligent automation for procedure analyses and failure impact analyses, by simulating the interactions between operations and systems with embedded failures. CONFIG models the actions taken by crew during space vehicle malfunctions and simulates how the planned action sequences in procedures affect a device model. Jointly the SPRAT and CONFIG projects provide an opportunity to investigate how the nature of a task affects the representation of actions, and to determine a more general action representation supporting a broad range of tasks. This paper describes the problems in representing actions for mission preparation and their relation to planning and scheduling.
Using Modem Design Tools for Digital Avionics Development Shrinking development time and increased complexity of new avionics forces the designer to use modem tools and methods during hardware development. Engineers at the Marshall Space Flight Center have successfully upgraded their design flow and used it to develop a Mongoose V based radiation tolerant processor board for the International Space Station's Water Recovery System. The design flow, based on hardware description languages, simulation, synthesis, hardware models, and full functional software model libraries, allowed designers to fully simulate the processor board from reset, through initialization before any boards were built. The fidelity of a digital simulation is limited to the accuracy of the models used and how realistically the designer drives the circuit's inputs during simulation. By using the actual silicon during simulation, device modeling errors are reduced. Numerous design flaws were discovered early in the design phase when they could be easily fixed. The use of hardware models and actual MIPS software loaded into full functional memory models also provided checkout of the software development environment. This paper will describe the design flow used to develop the processor board and give examples of errors that were found using the tools. An overview of the processor board firmware will also be covered.
Flowgraph models of thermal and electrical parameters interaction in solid state devices, examining performance characteristics, system stability, etc
The internal physical mechanism that governs the current conduction in junction-gate field effect transistors is studied. A numerical method of analyzing the devices with different length-to-width ratios and doping profiles is developed. This method takes into account the two dimensional character of the electric field and the field dependent mobility. Application of the method to various device models shows that the channel width and the carrier concentration in the conductive channel decrease with increasing drain-to-source voltage for conventional devices. It also shows larger differential drain conductances for shorter devices when the drift velocity is not saturated. The interaction of the source and the drain gives the carrier accumulation in the channel which leads to the space-charge-limited current flow. The important parameters for the space-charge-limited current flow are found to be the L/L sub DE ratio and the crossover voltage.
Many of the most challenging computational problems arising in practical applications are tackled by heuristic algorithms which have not been rigorously proven to outperform other approaches but rather have been empirically demonstrated to be effective. While quantum heuristics have been proposed since the early days of quantum computing, true empirical evaluation of the real-world performance of these algorithms is only becoming possible now as increasingly powerful quantum gate-model devices continue to come online.In this talk, I will give an overview of the NASA QuAIL team's ongoing investigation into quantum gate-model heuristic algorithms for exact and approximate optimization. In particular, we consider the performance of the Quantum Approximate Optimization Algorithm on NP-hard optimization problems, and describe algorithm parameter setting strategies for real-world quantum hardware. We then show a generalization of QAOA circuits, the Quantum Alternating Operator Ansatz, especially suitable for low-resource implementations of QAOA for problems with hard (feasibility) constraints. The talk will conclude with a discussion of research challenges, particularly for optimization and sampling applications of QAOA, and the potential of more general quantum heuristics to give advantages over classical computers.
Transport equations which describe the flow of holes and electrons in the heavily doped regions of a solar cell are presented in a form that is suitable for device modeling. Two experimentally determinable parameters, the effective bandgap shrinkage and the effective asymmetry factor are required to completely model the cell in these regions. Nevertheless, a knowledge of only the effective bandgap shrinkage is sufficient to model the terminal characteristics of the cell. The results of computer simulations of the effects of heavy doping are presented. The insensitivity of the terminal characteristics to the choice of effective asymmetry factor is shown along with the sensitivity of the electric field and quasielectric fields to this parameter. The dependence of the terminal characteristics on the effective bandgap shrinkage is also presented.
The activity in the field of photovoltaic semiconductor superstructures is described. Progress was accomplished in the two principal directions previously defined in our initial proposal, i.e.: (1) Theoretical investigation of the optical properties of superlattices; and (2) New solar cell concepts and device modeling. Although important information concerning the optical constants of superlattices and multiple quantum well structures was obtained from our computer model, most of the theoretical efforts have progressively shifted from the former to the latter aspect of the project because of the discovery of a new kind of photovoltaic device which may exhibit improved performances with respect to conventional solar cells.
Material imperfections, impurity clusters and fabrication defects across the back-surface-field junction can degrade the performance of high-efficiency solar cells. The degradation from defects appearing on the circumference of a solar cell is analyzed using a two-region developed perimeter device model. The width of the defective perimeter region is characterized by the range or the distance-of-influence of the defective edge and this width is about two diffusion lengths. The defective edge is characterized by a surface recombination velocity. Family of theoretical curves and numerical examples are presented to show that significant reduction of open-circuit voltage can occur in high-efficiency cells which are thin compared with the diffusion length. In one example, the degradation is decreased from 135 mV to 75 mV when the cell size is increased from 10 to 100 times the diffusion length in a thin cell whose thickness is 1% of the diffusion length.
The initial goal was to grow and characterize HgZnTe and determine if it indeed had the advantageous properties that were predicted. Researchers grew both bulk and liquid phase epitaxial HgZnTe. It was determined that HgZnTe had the following properties: (1) microhardness at least 50 percent greater than HgCdTe of equivalent bandgap; (2) Hg annealing rates of at least 2 to 4 times longer than HgCdTe; and (3) higher Hg vacancy formation energies. This early work did not focus on one specific composition (x-value) of HgZnTe since NASA was interested in HgZnTe's potential for a variety of applications. Since the beginning of 1989, researchers have been concentrating, however, on the liquid phase growth of very long wavelength infrared (VLWIR) HgZnTe (cutoff approx. equals 17 microns at 65K) to address the requirements of the Earth Observing System (EOS). Since there are no device models to predict the advantages in reliability one can gain with increased microhardness, surface stability, etc., one must fabricate HgZnTe detectors and assess their relative bake stability (accelerated life test behavior) compared with HgCdTe devices fabricated in the same manner. Researchers chose to fabricate HIT detectors as a development vehicle for this program because high performance in the VLWIR has been demonstrated with HgCdTe HIT detectors and the HgCdTe HIT process should be applicable to HgZnTe. HIT detectors have a significant advantage for satellite applications since these devices dissipate much less power than conventional photoconductors to achieve the same responsivity.
This paper reports the progress being made towards developing complete blood flow simulation capability in human, especially, in the presence of artificial devices such as valves and ventricular assist devices. Devices modeling poses unique challenges different from computing the blood flow in natural hearts and arteries. There are many elements needed such as flow solvers, geometry modeling including flexible walls, moving boundary procedures and physiological characterization of blood. As a first step, computational technology developed for aerospace applications was extended in the recent past to the analysis and development of mechanical devices. The blood flow in these devices is practically incompressible and Newtonian, and thus various incompressible Navier-Stokes solution procedures can be selected depending on the choice of formulations, variables and numerical schemes. Two primitive variable formulations used are discussed as well as the overset grid approach to handle complex moving geometry. This procedure has been applied to several artificial devices. Among these, recent progress made in developing DeBakey axial flow blood pump will be presented from computational point of view. Computational and clinical issues will be discussed in detail as well as additional work needed.
Special device modeling, design and layout, and precision processing controls were employed to fabricate new balanced-bridge 2x2 and 4x4 switches on X-cut, Y-propagation LiNbO3 substrate using Ti indiffused optical waveguides. The best of these devices achieved extinction ratio and crosstalk isolation of better than 93 dB electrically (46.5 dB optically). The new switches demonstrate good reproducibility with electrical crosstalk less than -80 dB.
The energy-efficient, environmentally friendly technology that will be presented is the result of a Space Act Agreement between -Technologies Worldwide, Inc., and the National Aeronautics and Space Administration s (NASA s) Marshall Space Flight Center (MSFC). This work combines semiconductor and printing technologies to advance lightweight electronic and photonic devices having excellent potential for commercial and exploration applications, and is an example of industry and government cooperation that leads to novel inventions. Device development involves three energy generation and consumption projects: 1) a low mass efficient (low power, low heat emission) micro light-emitting diode (LED) area lighting device; 2) a low-mass omni-directional efficient photovoltaic (PV) device with significantly improved energy capture; and 3) a new approach to building supercapacitors. These three technologies - energy capture, storage, and usage (e.g., lighting) - represent a systematic approach for building efficient local micro-grids that are commercially feasible; furthermore, these same technologies will be useful for lightweight power generation that enables inner planetary missions using smaller launch vehicles and facilitates surface operations. The PV device model is a two-sphere, light-trapped sheet approximately 2-mm thick. The model suggests a significant improvement over current thin film systems. All three components may be printed in line by printing sequential layers on a standard screen or flexographic direct impact press using the threedimensional printing technique (3DFM) patented by NthDegree. MSFC is testing the robustness of prototype devices in the harsh space and lunar surface environments, and available results will be reported. Unlike many traditional light sources, this device does not contain toxic compounds, and the LED component has passed stringent off-gassing tests required for potential manifesting on spacecraft such as the International Space Station. Future exploration missions will benefit from "green" technology lighting devices such as this, which show great promise for both terrestrial use and space missions.
Some attempts to produce, with an AP/C analytical plotter, stereo models using Mariner 9 pictures are reported. The first attempt using geometrically uncorrected mission test video system (MTVS) imagery failed; the second, using corrected reduced data record (RDR) pictures also failed, probably because they were reconstructed through a vidicon display which introduces additional distortion. By using images obtained from RDR tape data through the Optronics Photowrite device, models were successfully obtained.
The energy-efficient, environmentally friendly technology that will be presented is the result of a Space Act Agreement between NthDegree Technologies Worldwide, Inc., and the National Aeronautics and Space Administration's (NASA's) Marshall Space Flight Center (MSFC). The work combines semiconductor and printing technologies to advance lightweight electronic and photonic devices having excellent potential for commercial and exploration applications. Device development involves three projects that relate to energy generation and consumption: (1) a low-mass efficient (low power, low heat emission) micro light-emitting diode (LED) area lighting device; (2) a low-mass omni-directional efficient photovoltaic (PV) device with significantly improved energy capture; and (3) a new approach to building super-capacitors. These three technologies, energy capture, storage, and usage (e.g., lighting), represent a systematic approach for building efficient local micro-grids that are commercially feasible; furthermore, these same technologies, appropriately replacing lighting with lightweight power generation, will be useful for enabling inner planetary missions using smaller launch vehicles and to facilitate surface operations during lunar and planetary surface missions. The PV device model is a two sphere, light trapped sheet approximately 2-mm thick. The model suggests a significant improvement over current thin film systems. For lighting applications, all three technology components are printable in-line by printing sequential layers on a standard screen or flexographic direct impact press using the three-dimensional printing technique (3DFM) patented by NthDegree. One primary contribution to this work in the near term by the MSFC is to test the robustness of prototype devices in the harsh environments that prevail in space and on the lunar surface. It is anticipated that this composite device, of which the lighting component has passed off-gassing testing, will function appropriately in such environments consistent with NASA s exploration missions. Advanced technologies such as this show promise for both space flight and terrestrial applications.
New SAW sensors for integrated vehicle health monitoring of aerospace vehicles are being investigated. SAW technology is low cost, rugged, lightweight, and extremely low power. However, the lack of design tools for MEMS devices in general, and for Surface Acoustic Wave (SAW) devices specifically, has led to the development of tools that will enable integrated design, modeling, simulation, analysis and automatic layout generation of SAW devices. A frequency domain model has been created. The model is mainly first order, but it includes second order effects from triple transit echoes. This paper presents the model and results from the model for a SAW delay line device.
Semiconductor device profiles are determined by the characteristics of both etching and deposition processes. In particular, a highly anisotropic etch is required to achieve vertical sidewalls. However, etching is comprised of both anisotropic and isotropic components, due to ion and neutral fluxes, respectively. In Ar/Cl2 plasmas, for example, neutral chlorine reacts with the Si surfaces to form silicon chlorides. These compounds are then removed by the impinging ion fluxes. Hence the directionality of the ions (and thus the ion angular distribution function, or IAD), as well as the relative fluxes of neutrals and ions determines the amount of undercutting. One method of modeling device profile evolution is to simulate the moving solid-gas interface between the semiconductor and the plasma as a string of nodes. The velocity of each node is calculated and then the nodes are advanced accordingly. Although this technique appears to be relatively straightforward, extensive looping schemes are required at the profile corners. An alternate method is to use level set theory, which involves embedding the location of the interface in a field variable. The normal speed is calculated at each mesh point, and the field variable is updated. The profile comers are more accurately modeled as the need for looping algorithms is eliminated. The model we have developed is a 2-D Level Set Profile Evolution Simulation (LSPES). The LSPES calculates etch rates of a substrate in low pressure plasmas due to the incident ion and neutral fluxes. For a Si substrate in an Ar/C12 gas mixture, for example, the predictions of the LSPES are identical to those from a string evolution model for high neutral fluxes and two different ion angular distributions.(2) In the figure shown, the relative neutral to ion flux in the bulk plasma is 100 to 1. For a moderately isotropic ion angular distribution function as shown in the cases in the left hand column, both the LSPES (top row) and rude's string method (bottom row) predict tapered profiles. The LSPES uses an AD with a FWHM = 13.5 degrees, and rude's model uses a ratio of sheath voltage to ion temperature of 50. The more anisotropic IADs produce profiles with more vertical sidewalls and a wider bottom surface, as shown in the right hand column. Here, the LSPES has an AD with a FWHM = 2 degrees, and rude's model uses a ratio of 500 of sheath voltage to ion temperature. The agreement between the LSPES and rude's model is excellent in both cases. We will present etching profiles generated by the LSPES, including calculations of the re-emitted fluxes of both neutrals and ions off of the profile walls. In addition, we will show the effect of geometric structures (overhangs, etc.) on the etching profiles. Other physical aspects, such as surface diffusion, will also be included in the model.