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DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS2004

COTS MEMS Flow-Measurement Probes

As an alternative to conventional tubing instrumentation for measuring airflow, designers and technicians at Glenn Research Center have been fabricating packaging components and assembling a set of unique probes that contain commercial off-the-shelf (COTS) microelectromechanical systems (MEMS) sensor chips. MEMS sensor chips offer some compelling advantages over standard macroscopic measurement devices. MEMS sensor technology has matured through mass production and use in the automotive and aircraft industries. At present, MEMS are the devices of choice for sensors in such applications as tire-pressure monitors, altimeters, pneumatic controls, cable leak detectors, and consumer appliances. Compactness, minimality of power demand, rugged construction, and moderate cost all contribute to making MEMS sensors attractive for instrumentation for future research. Conventional macroscopic flow-measurement instrumentation includes tubes buried beneath the aerodynamic surfaces of wind-tunnel models or in wind-tunnel walls. Pressure is introduced at the opening of each such tube. The pressure must then travel along the tube before reaching a transducer that generates an electronic signal. The lengths of such tubes typically range from 20 ft (approx.= 6 m) to hundreds of feet (of the order of 100 m). The propagation of pressure signals in the tubes damps the signals considerably and makes it necessary to delay measurements until after test rigs have reached steady-state operation. In contrast, a MEMS pressure sensor that generates electronic output can take readings continuously under dynamic conditions in nearly real time. In order to use stainless-steel tubing for pressure measurements, it is necessary to clean many tubes, cut them to length, carefully install them, delicately deburr them, and splice them. A cluster of a few hundred 1/16-in.- (approx.=1.6-mm-) diameter tubes (such clusters are common in research testing facilities) can be several inches (of the order of 10 cm) in diameter and could weigh enough that two technicians are needed to handle it. Replacing hard tubing with electronic chips can eliminate much of the bulk. Each sensor would fit on the tip of a 1/16-in. tube with room to spare. The Lucas NovaSensor P592 piezoresistive silicon pressure sensor was chosen for this project because of its cost, availability, and tolerance to extreme ambient conditions. The sensor chip is 1 mm square by 0.6 mm thick (about 0.039 by 0.039 by 0.024 in.) and includes 0.12-mm (approx.=0.005-in.) wire connection tabs. The figure shows a flow-angularity probe that was built by use of three such MEMS chips. It is planned to demonstrate this MEMS probe as an alternative to a standard tube-type "Cobra" probe now used routinely in wind tunnels and aeronautical hardware. This MEMS probe could be translated across a flow field by use of a suitable actuator, so that its accuracy and the shortness of its response time could be exploited to obtain precise dynamic measurements of a sort that cannot be made by use of conventional tubing-based instrumentation.

Redding, Chip↗

DOE OSTI2020

W-band system-on-chip electron cyclotron emission imaging system on DIII-D

Monolithic, millimeter wave “system-on-chip” (SoC) technology has been employed in heterodyne receiver integrated circuit radiometers in a newly developed Electron Cyclotron Emission Imaging (ECEI) system on the DIII-D tokamak for 2D electron temperature profile and fluctuation evolution diagnostics. Here, a prototype module operating in E-band (72-80 GHz) was first employed in a 2 x 10 element array that demonstrated significant improvements over the previous quasi-optical Schottky diode mixer arrays during the 2018 operational campaign of the DIII-D tokamak. For compatibility with International Thermonuclear Experimental Reactor (ITER) relevant scenarios on DIII-D, the SoC ECEI system was upgraded with 20 horn-waveguide receiver modules. Each individual module contains a University of California at Davis designed W-band (75 -110 GHz) receiver die that integrates a broadband low noise amplifier (LNA), a double balanced down-converting mixer, and a x4 multiplier on the local oscillator (LO) chain. A x2 multiplier and two IF amplifiers are packaged and selected to further boost the signal strength as well as downconvert the signal frequency. The upgraded W-band array exhibits > 30 dB additional gain and 20x improvement in noise temperature comparing with the previous Schottky diode radio frequency (RF) mixer input systems; an internal 8 times multiplier chain is used to bring down the LO frequency below 12 GHz, thereby obviating the need for a large aperture for quasi-optical LO coupling and replacing it with coaxial connectors. The horn-waveguide shielding housing avoids out-of-band noise interference on each individual module. The upgraded ECEI system plays an important role for absolute electron temperature evolution and fluctuation measurements for edge and core region transport physics studies.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

NASA NTRS2006

Deep Space Network, Cryogenic HEMT LNAs

Exploration of the Solar System with automated spacecraft that are more than ten astronomical units (1 AU = 149,597,870.691 km) from earth requires very large antennae employing extremely sensitive receivers. A key figure of merit in the specification of the spacecraft-to-earth telecommunications link is the ratio of the antenna gain to operatio nal noise temperature (G/Top) of the system. The Deep Space Network (DSN) receivers are cryogenic, low-noise amplifiers (LNAs) which addres s the need to maintain Top as low as technology permits. Historicall y, the extra-ordinarily sensitive receive systems operated by the DSN have required ctyogenically cooled, ruby masers, operating at a physi cal temperature near the boiling point of helium, as the LNA. Althoug h masers continue to be used today, they are hand crafted at JPL and expensive to manufacture and maintain. Recent advances in the developm ent of indium phosphide (InP) based high electron mobility transistor s (HEMTs) combined with cryogenic cooling near the boiling point of h ydrogen have made this alternate technology comparable with and a fraction of the cost of maser technology. InP HEMT LNA modules are demons trating noise temperatures less than ten times the quantum noise limi t (10hf/k) from 1 to 100 GHz. To date, the lowest noise LNA modules developed for the DSN have demonstrated noise temperatures of 3.5 K and 8.5 K at 8.5 K at 32 GHz, respectively. Front-end receiver packages employing these modules have demonstrated operating system noise temperatures of 17 K at 8.4 GHz (on a 70m antenna at zenith) and 39 K at 3 2 GHz (on a 34m antenna at zenith). The development and demonstration of cryogenic, InP HEMT based front-end amplifiers for the DSN requir es accurate component and module characterization, and modeling from 1 to 100 GHz at physical temperatures down to 12 K. The characterizati on and modeling begins with the HEMT chip, proceeds to the multi-stag e HEMT LNA module, and culminates with the complete front-end cryogenic receiver package for the antenna. This presentation will provide a n overview of this development process. Examples will be shown for de vices, LNA modules, front-end receiver packages, antennae employing these packages and the improvements to the down-link capacity.

low-noise amplifiers (LNAs)↗

NASA NTRS2008

Evaluation of Silicon-on-Insulator HTOP-01 Operational Amplifier for Wide Temperature Operation

Electronics capable of operation under extreme temperatures are required in many of NASA space exploration missions. Aerospace and military applications, as well as some terrestrial industries constitute environments where electronic systems are anticipated to be exposed to extreme temperatures and wide-range thermal swings. Electronics that are able to withstand and operate efficiently in such harsh environments would simplify, if not eliminate, traditional thermal control elements and their associated structures for proper ambient operation. As a result, overall system mass would be reduced, design would be simplified, and reliability would be improved. Electronic parts that are built utilizing silicon-on-insulator (SOI) technology are known to offer better radiation-tolerance compared to their conventional silicon counterparts, provide faster switching, and consume less power. They also exhibit reduced leakage current and, thus, they are often tailored for high temperature operation. These attributes make SOI-based devices suitable for use in harsh environments where extreme temperatures and wide thermal swings are anticipated. A new operational amplifier, based on silicon-on-insulator technology and geared for high temperature well-logging applications, was recently introduced by Honeywell Corporation. This HTOP-01 dual precision operational amplifier is a low power device, operates on a single supply, and has an internal oscillator and an external clocking option [1]. It is rated for operation from -55 C to +225 C with a maximum output current capability of 50 mA. The amplifier chip is designed as a 14-pin, hermetically-sealed device in a ceramic package. Table I shows some of the device manufacturer s specifications.

Patterson, Richard↗

NASA NTRS2018

2.5/3D Daisy Chain Reliability Evaluation

The objective of this task is to evaluate thermal cycle behavior of advanced 2.5/3D electronics — commercial-off the-shelf (COTS) —packages of different configurations assembled onto printed circuit boards (PCBs). Three key approaches were considered for evaluation. The first approach focused on the through-mold via (TMV™) technology at assembly level. The second approach focused on evaluation of 2.5D (also known as, System in Package (SiP)) in fine pitch ball grid array (FPGA). The third approach focused on evaluation of through-silicone-via (TSV) technologies. This report presents the test results for TMV™ and SiP packaging technologies and reliability, and it also provides lessons learned on quality assurance methods. Specifically, the report presents the test matrix for various 3D TMV™ packaging assembly configurations and reliability characterizations performed under two accelerated thermal cycling (ATC) and accelerated thermal shock cycling (ATSC) conditions. The ATC and ATSC were performed in the range of –55°C to 125°C and –100°C to 100°C, respectively. The report also includes assembly of a SiP— a 60-mm fine-pitch ball-grid array (FPGA) interposer with an IC at the center and six chip-scale package (CSP) daisy chains at the periphery—with package assembly characterizations. After assembly, the daisy chains were subjected to ATCs in the range of –40°C to 125°C for reliability evaluation. Finally, for both TMV™ and SiP packaging configurations, characterizations results by X-ray, optical imaging, and daisy-chain resistance evaluations were also presented.

Ghaffarian, Reza↗

NASA NTRS2008

Performance of MEMS Silicon Oscillator, ASFLM1, under Wide Operating Temperature Range

Over the last few years, MEMS (Micro-Electro-Mechanical Systems) resonator-based oscillators began to be offered as commercial-off-the-shelf (COTS) parts by a few companies [1-2]. These quartz-free, miniature silicon devices could compete with the traditional crystal oscillators in providing the timing (clock function) for many digital and analog electronic circuits. They provide stable output frequency, offer great tolerance to shock and vibration, and are immune to electro-static discharge [1-2]. In addition, they are encapsulated in compact lead-free packages, cover a wide frequency range (1 MHz to 125 MHz), and are specified, depending on the grade, for extended temperature operation from -40 C to +85 C. The small size of the MEMS oscillators along with their reliability and thermal stability make them candidates for use in space exploration missions. Limited data, however, exist on the performance and reliability of these devices under operation in applications where extreme temperatures or thermal cycling swings, which are typical of space missions, are encountered. This report presents the results of the work obtained on the evaluation of an ABRACON Corporation MEMS silicon oscillator chip, type ASFLM1, under extreme temperatures.

Patterson, Richard L.↗

NASA NTRS2014

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Ghaffarian, Reza↗

NASA NTRS2011

BOK-Underfill Optimization for FPGA Package/Assembly

Commercial-off-the-shelf area array package technologies in high-reliability versions are being considered for NASA electronic systems. These packages are prone to early failure due to the severe mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of ball interconnections decrease, susceptibility to mechanical loading and cycling fatigue grows. This report presents a summary of the body of knowledge developed for the evaluation of area array packages and is based on surveys of literature from industry and academia. For high-reliability applications, the limited data that exists will be presented. Most data from industry deals with mechanical fatigue caused by four-point bend tests, as well as from drop tests for hand-held electronics; the most recent data will be presented, along with a brief background of prior literature. Understanding the key design guidelines and failure mechanisms from past tests is critical to developing an approach that will minimize future failures. Additional specific testing enables low-risk insertion of these advanced electronic packages.

mechanical fatigue↗

NASA NTRS2009

Assessment of Operation of EMK21 MEMS Silicon Oscillator Over Wide Temperature Range

Electronic control systems, data-acquisition instrumentation, and microprocessors require accurate timing signals for proper operation. Traditionally, ceramic resonators and crystal oscillators provided this clock function for the majority of these systems. Over the last few years, MEMS (Micro-Electro-Mechanical Systems) resonator-based oscillators began to surface as commercial-off-the-shelf (COTS) parts by a few companies. These quartz-free, miniature silicon devices could easily replace the traditional crystal oscillators in providing the timing/clock function for many digital and analog circuits. They are reported to provide stable output frequency, offer great tolerance to shock and vibration, and are immune to electro-static discharge [ 1-2]. In addition, they are encapsulated in compact lead-free packages and cover a wide frequency range (1 MHz to 125 MHz). The small size of the MEMS oscillators along with their thermal stability make them ideal candidates for use in space exploration missions. Limited data, however, exist on the performance and reliability of these devices under operation in applications where extreme temperatures or thermal cycling swings, which are typical of space missions, are encountered. This report presents the results of the work obtained on the evaluation of an Ecliptek Corporation MEMS silicon oscillator chip under extreme temperatures.

Patterson, Richard L.↗

NASA NTRS2010

Demonstration of a Submillimeter-Wave HEMT Oscillator Module at 330 GHz

In this work, radial transitions have been successfully mated with a HEMT-based MMIC (high-electron-mobility-transistor-based monolithic microwave integrated circuit) oscillator circuit. The chip has been assembled into a WR2.2 waveguide module for the basic implementation with radial E-plane probe transitions to convert the waveguide mode to the MMIC coplanar waveguide mode. The E-plane transitions have been directly integrated onto the InP substrate to couple the submillimeter-wave energy directly to the waveguides, thus avoiding wire-bonds in the RF path. The oscillator demonstrates a measured 1.7 percent DC-RF efficiency at the module level. The oscillator chip uses 35-nm-gate-length HEMT devices, which enable the high frequency of oscillation, creating the first demonstration of a packaged waveguide oscillator that operates over 300 GHz and is based on InP HEMT technology. The oscillator chip is extremely compact, with dimensions of only 1.085 x 320 sq mm for a total die size of 0.35 sq mm. This fully integrated, waveguide oscillator module, with an output power of 0.27 mW at 330 GHz, can provide low-mass, low DC-power-consumption alternatives to existing local oscillator schemes, which require high DC power consumption and large mass. This oscillator module can be easily integrated with mixers, multipliers, and amplifiers for building high-frequency transmit and receive systems at submillimeter wave frequencies. Because it requires only a DC bias to enable submillimeter wave output power, it is a simple and reliable technique for generating power at these frequencies. Future work will be directed to further improving the applicability of HEMT transistors to submillimeter wave and terahertz applications. Commercial applications include submillimeter-wave imaging systems for hidden weapons detection, airport security, homeland security, and portable low-mass, low-power imaging systems

Radisic, Vesna↗

NASA NTRS2010

Effects of Temperature on the Performance and Stability of Recent COTS Silicon Oscillators

Silicon oscillators have lately emerged to serve as potential replacement for crystal and ceramic resonators to provide timing and clock signals in electronic systems. These semiconductor-based devices, including those that are based on MEMS technology, are reported to be resistant to vibration and shock (an important criteria for systems to be deployed in space), immune to EMI, consume very low current, require few or no external components, and cover a wide range of frequency for analog and digital circuits. In this work, the performance of five recently-developed COTS silicon oscillator chips from different manufacturers was determined within a temperature range that extended beyond the individual specified range of operation. In addition, restart capability at extreme temperatures, i.e. power switched on while the device was soaking at extreme (hot or cold) temperature, and the effects of thermal cycling under a wide temperature range on the operation of these silicon oscillators were also investigated. Performance characterization of each oscillator was obtained in terms of its output frequency, duty cycle, rise and fall times, and supply current at specific test temperatures. The five different oscillators tested operated beyond their specified temperature region, with some displaying excellent stability throughout the whole test temperature range. Others experienced some instability at certain temperature test points as evidenced by fluctuation in the output frequency. Recovery from temperature-induced changes took place when excessive temperatures were removed. It should also be pointed out that all oscillators were able to restart at the extreme test temperatures and to withstand the limited thermal cycling without undergoing any significant changes in their characteristics. In addition, no physical damage was observed in the packaging material of any of these silicon oscillators due to extreme temperature exposure and thermal cycling. It is recommended that additional and more comprehensive testing under long term cycling be carried out to fully establish the reliability of these devices and to determine their suitability for use in space exploration missions under extreme temperature conditions.

Patterson, Richard L.↗

NASA NTRS2018

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

microchannel↗

DOE OSTI2024

Giant energy storage and power density negative capacitance superlattices

Dielectric electrostatic capacitors, because of their ultrafast charge-discharge, are desirable for high-power energy storage applications. Along with ultrafast operation, on-chip integration can enable miniaturized energy storage devices for emerging autonomous microelectronics and microsystems. Moreover, state-of-the-art miniaturized electrochemical energy storage systems-microsupercapacitors and microbatteries-currently face safety, packaging, materials and microfabrication challenges preventing on-chip technological readiness, leaving an opportunity for electrostatic microcapacitors. Here, in this study, we report record-high electrostatic energy storage density (ESD) and power density, to our knowledge, in HfO 2 -ZrO 2 -based thin film microcapacitors integrated into silicon, through a three-pronged approach. First, to increase intrinsic energy storage, atomic-layer-deposited antiferroelectric HfO 2 -ZrO 2 films are engineered near a field-driven ferroelectric phase transition to exhibit amplified charge storage by the negative capacitance effect, which enhances volumetric ESD beyond the best-known back-end-of-the-line-compatible dielectrics (115 J cm -3 ). Second, to increase total energy storage, antiferroelectric superlattice engineering scales the energy storage performance beyond the conventional thickness limitations of HfO 2 -ZrO 2 -based (anti)ferroelectricity (100-nm regime). Third, to increase the storage per footprint, the superlattices are conformally integrated into three-dimensional capacitors, which boosts the areal ESD nine times and the areal power density 170 times that of the best-known electrostatic capacitors: 80 mJ cm -2 and 300 kW cm -2 , respectively. This simultaneous demonstration of ultrahigh energy density and power density overcomes the traditional capacity-speed trade-off across the electrostatic-electrochemical energy storage hierarchy. Furthermore, the integration of ultrahigh-density and ultrafast-charging thin films within a back-end-of-the-line-compatible process enables monolithic integration of on-chip microcapacitors, which can unlock substantial energy storage and power delivery performance for electronic microsystems.

25 ENERGY STORAGE↗

NASA NTRS2007

Flight Qualified Micro Sun Sensor

A prototype small, lightweight micro Sun sensor (MSS) has been flight qualified as part of the attitude-determination system of a spacecraft or for Mars surface operations. The MSS has previously been reported at a very early stage of development in NASA Tech Briefs, Vol. 28, No. 1 (January 2004). An MSS is essentially a miniature multiple-pinhole electronic camera combined with digital processing electronics that functions analogously to a sundial. A micromachined mask containing a number of microscopic pinholes is mounted in front of an active-pixel sensor (APS). Electronic circuits for controlling the operation of the APS, readout from the pixel photodetectors, and analog-to-digital conversion are all integrated onto the same chip along with the APS. The digital processing includes computation of the centroids of the pinhole Sun images on the APS. The spacecraft computer has the task of converting the Sun centroids into Sun angles utilizing a calibration polynomial. The micromachined mask comprises a 500-micron-thick silicon wafer, onto which is deposited a 57-nm-thick chromium adhesion- promotion layer followed by a 200-nm-thick gold light-absorption layer. The pinholes, 50 microns in diameter, are formed in the gold layer by photolithography. The chromium layer is thin enough to be penetrable by an amount of Sunlight adequate to form measurable pinhole images. A spacer frame between the mask and the APS maintains a gap of .1 mm between the pinhole plane and the photodetector plane of the APS. To minimize data volume, mass, and power consumption, the digital processing of the APS readouts takes place in a single field-programmable gate array (FPGA). The particular FPGA is a radiation- tolerant unit that contains .32,000 gates. No external memory is used so the FPGA calculates the centroids in real time as pixels are read off the APS with minimal internal memory. To enable the MSS to fit into a small package, the APS, the FPGA, and other components are mounted on a single two-sided board following chip-on-board design practices

Liebe, Carl Christian↗

NASA NTRS2007

SiC Multi-Chip Power Modules as Power-System Building Blocks

The term "SiC MCPMs" (wherein "MCPM" signifies "multi-chip power module") denotes electronic power-supply modules containing multiple silicon carbide power devices and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking. Moreover, the higher-temperature capabilities of SiC MCPMs could enable operation in environments hotter than Si-based power systems can withstand. The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules. In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications: typical functions could include regulating voltages, storing energy, and driving motors. Because identical SiC MCPM building blocks could be utilized in a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. Several prototype DC-to-DC power-converter modules containing SiC power-switching devices were designed and built to demonstrate the feasibility of the SiC MCPM concept. In anticipation of a future need for operation at high temperature, the circuitry in the modules includes high-temperature inductors and capacitors. These modules were designed to be stacked to construct a system of four modules electrically connected in series and/or parallel. The packaging of the modules is designed to satisfy requirements for series and parallel interconnection among modules, high power density, high thermal efficiency, small size, and light weight. Each module includes four output power connectors two for serial and two for parallel output power connections among the modules. Each module also includes two signal connectors, electrically isolated from the power connectors, that afford four zones for signal interconnections among the SOI controllers. Finally, each module includes two input power connectors, through which it receives power from an in-line power bus. This design feature is included in anticipation of a custom-designed power bus incorporating sockets compatible with snap-on type connectors to enable rapid replacement of failed modules.

Lostetter, Alexander↗

NASA NTRS2008

Update on Development of SiC Multi-Chip Power Modules

Progress has been made in a continuing effort to develop multi-chip power modules (SiC MCPMs). This effort at an earlier stage was reported in 'SiC Multi-Chip Power Modules as Power-System Building Blocks' (LEW-18008-1), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 28. The following recapitulation of information from the cited prior article is prerequisite to a meaningful summary of the progress made since then: 1) SiC MCPMs are, more specifically, electronic power-supply modules containing multiple silicon carbide power integrated-circuit chips and silicon-on-insulator (SOI) control integrated-circuit chips. SiC MCPMs are being developed as building blocks of advanced expandable, reconfigurable, fault-tolerant power-supply systems. Exploiting the ability of SiC semiconductor devices to operate at temperatures, breakdown voltages, and current densities significantly greater than those of conventional Si devices, the designs of SiC MCPMs and of systems comprising multiple SiC MCPMs are expected to afford a greater degree of miniaturization through stacking of modules with reduced requirements for heat sinking; 2) The stacked SiC MCPMs in a given system can be electrically connected in series, parallel, or a series/parallel combination to increase the overall power-handling capability of the system. In addition to power connections, the modules have communication connections. The SOI controllers in the modules communicate with each other as nodes of a decentralized control network, in which no single controller exerts overall command of the system. Control functions effected via the network include synchronization of switching of power devices and rapid reconfiguration of power connections to enable the power system to continue to supply power to a load in the event of failure of one of the modules; and, 3) In addition to serving as building blocks of reliable power-supply systems, SiC MCPMs could be augmented with external control circuitry to make them perform additional power-handling functions as needed for specific applications. Because identical SiC MCPM building blocks could be utilized in such a variety of ways, the cost and difficulty of designing new, highly reliable power systems would be reduced considerably. This concludes the information from the cited prior article. The main activity since the previously reported stage of development was the design, fabrication, and testing a 120- VDC-to-28-VDC modular power-converter system composed of eight SiC MCPMs in a 4 (parallel)-by-2 (series) matrix configuration, with normally-off controllable power switches. The SiC MCPM power modules include closed-loop control subsystems and are capable of operating at high power density or high temperature. The system was tested under various configurations, load conditions, load-transient conditions, and failure-recovery conditions. Planned future work includes refinement of the demonstrated modular system concept and development of a new converter hardware topology that would enable sharing of currents without the need for communication among modules. Toward these ends, it is also planned to develop a new converter control algorithm that would provide for improved sharing of current and power under all conditions, and to implement advanced packaging concepts that would enable operation at higher power density.

Lostetter, Alexander↗