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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Designing for Small Volume Assembly of Advanced Electronics Packages

We describe a general methodology to Design for Producibility and Reliability (DFPAR) for very small volume production runs. In cases where the entire volume for fabrication is less than five products, traditional Statistical Process Control (SPC) is inadequate due to reliance on statistics of much larger volumes and the Central Limit Theorem. Data acquisition for process parameter estimation from such a small sample size is difficult; however, it is critical to producing high reliability product.

Central Limit Theorem statistics high reliability ↗
NASA NTRS1970

Electronic packaging and cabling

Testing electrical, mechanical, and handling properties and environmental characteristics of small gage electrical wire for interplanetary spacecraft

Source record↗
NASA NTRS1975

Thermal control of power supplies with electronic packaging techniques

The analysis, design, and development work to reduce the weight and size of a standard modular power supply with a 350 watt output was summarized. By integrating low cost commercial heat pipes in the redesign of this power supply, weight was reduced by 30% from that of the previous design. The temperature was also appreciably reduced, increasing the environmental capability of the unit. A demonstration unit with a 100 watt output and a 15 volt regulator module, plus simulated output modules, was built and tested to evaluate the thermal performance of the redesigned power supply.

Source record↗
NASA NTRS1977

Thermal control of power supplies with electronic packaging techniques

The integration of low-cost commercial heat pipes in the design of a NASA candidate standard modular power supply with a 350 watt output resulted in a 44% weight reduction. Part temperatures were also appreciably reduced, increasing the environmental capability of the unit. A complete 350- watt modular power converter was built and tested to evaluate thermal performance of the redesigned supply.

Source record↗
NASA NTRS1999

Electronic Packaging for Space Applications Workshop 1999

This paper presents viewgraphs on the Commercial Off-The-Shelf (COTS) Program. The topics include: 1) Advocacy for COTS; 2) MARS01 Program/Requirements; 3) MARS01 COTS Screening Flow; 4) Test Results-Electrical, C-Sam, Burn-In; 5) Value Added Analysis (Risk Reduction); 6) Value Added Analysis (Cost); 7) Impact of COTS ++ Screening and 8) Summary.

Sandor, Mike↗
NASA NTRS2009

Deep Impact Delta II Launch Vehicle Cracked Thick Film Coating on Electronic Packages Technical Consultation Report

The Deep Impact spacecraft was launched on a Boeing Delta II rocket from Cape Canaveral Air Force Station (CCAFS) on January 12, 2005. Prior to the launch, the Director of the Office of Safety and Mission Assurance (OS&MA) requested the NASA Engineering and Safety Center (NESC) lead a team to render an independent opinion on the rationale for flight and the risk code assignments for the hazard of cracked Thick Film Assemblies (TFAs) in the E-packages of the Delta II launch vehicle for the Deep Impact Mission. The results of the evaluation are contained in this report.

Cameron, Kenneth D.↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗
NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗