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NASA NTRS2002

Simulation Model of A Ferroelectric Field Effect Transistor

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

MacLeod, Todd C.↗

NASA NTRS2003

Interplay Between Thin Film Ferroelectric Composition, Microstructure and Microwave Phase Shifter Performance

One of the keys to successfully incorporating ferroelectric films into Ku-band (12 to 18 GHz) phase shifters is to establish the composition, microstructure, and thickness required to meet the tuning needs, and tailor the film properties to meet these needs. Optimal performance is obtained when the film composition and device design are such that the device performance is limited by odd mode dielectric losses, and these losses are minimized as much as possible while still maintaining adequate tunability. The parameters required to maintain device performance will vary slightly depending on composition, but we can conclude that the best tuning-to-loss figures of merit (K-factor) are obtained when there is minimal variation between the in-plane and out-of-plane lattice parameters, and the full-width half maximum values of the BSTO (002) peaks are less than approximately 0.04 deg. We have observed that for phase shifters in which the ferroelectric crystalline quality and thickness are almost identical, higher losses are observed in films with higher BaISr ratios. The best performance was observed in phase shifters with Ba:Sr = 30:70. The superiority of this composition was attributed to several interacting factors: the B a: Sr ratio was such that the Curie temperature (180 K) was far removed from room temperature, the crystalline quality of the film was excellent, and there was virtually no difference between the inplane and out-of-plane lattice parameters of the film.

Mueller, Carl H.↗

NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗

NASA NTRS2004

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Phillips, Thomas A.↗

NASA NTRS2004

Optimization of Thin Film Ferroelectrics for Communication Applications

The application of thin film ferroelectrics for the development of tunable microwave components have been a very active field of investigation thraughout the last decade. This presentation will provide an overview of some of the activities in the aforementioned area by other research groups and the current status of the field. In particular, we will discuss the efforts currently underway at the NASA Glenn Research Center in the area of phase shifter development using Ba2Sr(1-x)TiO3 ferroelectric thin films. Emphasis will be given to the approaches that have been investigated in order to improve the performance (i.e., figure of merit) of these devices. Some of these approaches deal with the details of circuit design parameters, while others are related to Experimental results and discussions on the aforementioned topics will be presented the optimization of material properties through different deposition techniques.

Miranda, Felix A.↗

NASA NTRS2003

Continuous Optimization of Thin Film Ferroelectrics for Tunable Microwave Devices for Communications Applications

During the last decades thin film ferroelectrics have been investigated in great detail because of their versatility and advantages for tunable devices. Many reports on tunable components such as resonators, filters, oscillators and phase shifters have been published by researchers all around world. These efforts have shed light on the primary advantages as well as the current shortcomings of these materials that should be considered for the development of practical microwave devices and systems. In this paper, we intend to discuss the most relevant outcomes of current collaborations taking place at the NASA Glenn Research Center aimed at improving the quality of ferroelectric microwave components (e.g., phase shifters) via careful processing and evaluation of the materials properties of the thin films. To the extent that our applications allow, we have worked with fixed circuit configurations to determine which material modifications are of most impact to the performance of a given circuit. Examples on the improvements on the performance of these circuits will be provided.

Miranda, Felix A.↗

NASA NTRS2005

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Phillips, Thomas A.↗

NASA NTRS2006

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Phillips, Thomas A.↗

NASA NTRS1993

Thin film ferroelectric electro-optic memory

An electrically programmable, optically readable data or memory cell is configured from a thin film of ferroelectric material, such as PZT, sandwiched between a transparent top electrode and a bottom electrode. The output photoresponse, which may be a photocurrent or photo-emf, is a function of the product of the remanent polarization from a previously applied polarization voltage and the incident light intensity. The cell is useful for analog and digital data storage as well as opto-electric computing. The optical read operation is non-destructive of the remanent polarization. The cell provides a method for computing the product of stored data and incident optical data by applying an electrical signal to store data by polarizing the thin film ferroelectric material, and then applying an intensity modulated optical signal incident onto the thin film material to generate a photoresponse therein related to the product of the electrical and optical signals.

Thakoor, Sarita↗

NASA NTRS2001

A-site- and/or B-site-modified PbZrTiO3 materials and (Pb, Sr, Ca, Ba, Mg) (Zr, Ti, Nb, Ta)O3 films having utility in ferroelectric random access memories and high performance thin film microactuators

A modified PbZrTiO.sub.3 perovskite crystal material thin film, wherein the PbZrTiO.sub.3 perovskite crystal material includes crystal lattice A-sites and B-sites at least one of which is modified by the presence of a substituent selected from the group consisting of (i) A-site substituents consisting of Sr, Ca, Ba and Mg, and (ii) B-site substituents selected from the group consisting of Nb and Ta. The perovskite crystal thin film material may be formed by liquid delivery MOCVD from metalorganic precursors of the metal components of the thin film, to form PZT and PSZT, and other piezoelectric and ferroelectric thin film materials. The thin films of the invention have utility in non-volatile ferroelectric memory devices (NV-FeRAMs), and in microelectromechanical systems (MEMS) as sensor and/or actuator elements, e.g., high speed digital system actuators requiring low input power levels.

Roeder, Jeffrey F.↗

NASA NTRS2004

A-SITE-AND/OR B-SITE-MODIFIED PBZRTIO3 MATERIALS AND (PB, SR, CA, BA, MG) (ZR, TI,NB, TA)O3 FILMS HAVING UTILITY IN FERROELECTRIC RANDOM ACCESS MEMORIES AND HIGH PERFORMANCE THIN FILM MICROACTUATORS

Roeder, Jeffrey F.↗

NASA NTRS1977

Ferroelectric liquid crystal display

A ferroelectric liquid crystal display device employs capacitance spoiling layers to minimize unneeded capacitances created by crossovers of X and Y address lines and to accurately define desired capacitances. The spoiler layers comprise low dielectric constant layers which space electrodes from the ferroelectric at crossover points where capacitance is not needed for device operation.

York, Paul K.↗

NASA NTRS1979

One-third selection scheme for addressing a ferroelectric matrix arrangement

An improved scheme for selectively addressing a matrix arrangement comprised of ferroelectrics having x and y orthogonally disposed intersecting lines. A one-third selection scheme is utilized that includes normalized selection signals having amplitudes: V.sub.x =0; V.sub.x =2/3; V.sub.y =1/3; and V.sub.y =1, which signals can be applied to the intersection of an x and y-line. The instant selection scheme minimizes both hysteresis creep and the cross-coupling voltage between x and y-lines to prevent undesirable hysteresis switching of the ferroelectric matrix arrangement.

Tannas, Jr., Lawrence E.↗

NASA NTRS2010

Characterization of a Common-Source Amplifier Using Ferroelectric Transistors

This paper presents empirical data that was collected through experiments using a FeFET in the established common-source amplifier circuit. The unique behavior of the FeFET lends itself to interesting and useful operation in this widely used common-source amplifier. The paper examines the effect of using a ferroelectric transistor for the amplifier. It also examines the effects of varying load resistance, biasing, and input voltages on the output signal and gives several examples of the output of the amplifier for a given input. The difference between a commonsource amplifier using a ferroelectric transistor and that using a MOSFET is addressed.

Hunt, Mitchell↗

NASA NTRS2010

Switching Characteristics of Ferroelectric Transistor Inverters

This paper presents the switching characteristics of an inverter circuit using a ferroelectric field effect transistor, FeFET. The propagation delay time characteristics, phl and plh are presented along with the output voltage rise and fall times, rise and fall. The propagation delay is the time-delay between the V50% transitions of the input and output voltages. The rise and fall times are the times required for the output voltages to transition between the voltage levels V10% and V90%. Comparisons are made between the MOSFET inverter and the ferroelectric transistor inverter.

Laws, Crystal↗

NASA NTRS2011

Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

John, Caroline S.↗

NASA NTRS2011

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

Mitchell, Cody↗

NASA NTRS2013

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Hunt, Mitchell↗