Design and performance of two integrated circuits for fluidic-controlled pneumatic stepping motor system
Fluidic integrated circuits for control of pneumatic stepping-motor actuator system
Dustin, M. O.↗
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Custom metallized multigate array, section 2 Interim technical report
Reliability engineering processes for custom metallized multigate integrated circuit array design
Source record↗
Custom metallized multigate array, section 1 Interim technical report
Custom metallized multigate integrated circuit array design
Source record↗
C-MOS array design techniques Final quarterly report, 15 Sep. - 15 Dec. 1970
Design and performance of logic circuit chip for computerized design of MOS integrated circuit arrays
Feller, A.↗
Universal dc signal conditioner
Signal conditioner was designed which can condition dc signals over range of + or - volts. It is lighter, has lower initial and maintenance costs, and higher reliability than conventional discrete circuit designs. System incorporates linear integrated circuits in conjunction with hybrid, thin film circuit technology to achieve high degree of circuit miniaturization.
Bradanini, P. A.↗
Monolithic parallel processor, phase 1A
A four-bit parallel processor LSI array was designed and fabricated using COS/MOS integrated-circuit technology. The design features include the provision for interconnecting groups of parallel-processor chips to form an expanded processor of any desired word length. This 800-transistor "computer on a chip' circuit has the logic capability of a medium-size, medium-speed, general-purpose computer suitable for sophisticated scientific data processing. The ability to fabricate this device repetitively was demonstrated.
Source record↗
Minimizing the area required for time constants in integrated circuits
When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.
Lyons, J. C.↗
Process development of beam-lead silicon-gate COS/MOS integrated circuits
Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.
Baptiste, B.↗
CADAT integrated circuit mask analysis
CADAT System Mask Analysis Program (MAPS2) is automated software tool for analyzing integrated-circuit mask design. Included in MAPS2 functions are artwork verification, device identification, nodal analysis, capacitance calculation, and logic equation generation.
Source record↗
Developing new architectures for the Block 2 VLBI correlator system
The overall LSI (large-scale integrated circuits) architecture design and current status of the VBLI (very long baseline interferometry) block 2 correlator is addressed. The VBLI correlator algorithms demand a computing system that provides a throughput of hundreds of millions of instructions per second to perform cross-correlation detection for six baselines. The LSI technology lights the way for the computation of complex parallel process and is raising the upper bound of computerization.
Peterson, J. C.↗
Diode multipliers for submillimeter-wave InAlAs/InGaAs heterostructure monolithic integrated circuits
InAlAs/InGaAs heterostructures are studied as multiplier elements for submillimeter-wave monolithic integrated circuits. The designs considered for this purpose are based on the principle of conventional HEMT, HEMT with n+ bottom layer, and a new proposed scheme of quantum-confined modulated charge (QCMC). The QCMC diode is analyzed theoretically and experimentally showing its potential operation capability at 1.5 THz.
Kwon, Y.↗
Layout optimization with algebraic multigrid methods
Finding the optimal position for the individual cells (also called functional modules) on the chip surface is an important and difficult step in the design of integrated circuits. This paper deals with the problem of relative placement, that is the minimization of a quadratic functional with a large, sparse, positive definite system matrix. The basic optimization problem must be augmented by constraints to inhibit solutions where cells overlap. Besides classical iterative methods, based on conjugate gradients (CG), we show that algebraic multigrid methods (AMG) provide an interesting alternative. For moderately sized examples with about 10000 cells, AMG is already competitive with CG and is expected to be superior for larger problems. Besides the classical 'multiplicative' AMG algorithm where the levels are visited sequentially, we propose an 'additive' variant of AMG where levels may be treated in parallel and that is suitable as a preconditioner in the CG algorithm.
Regler, Hans↗
Innovation and application of ANN in Europe demonstrated by Kohonen maps
One of the most important contributions to neural networks comes from Kohonen, Helsinki/Espoo, Finland, who had the idea of self-organizating maps in 1981. He verified his idea by an algorithm of which many applications make use of. The impetus for this idea came from biology, a field where the Europeans have always been very active at several research laboratories. The challenge was to model the self-organization found in the brain. Today one goal is the development of more sophisticated neurons which model the biological neurons more exactly. They should come to a better performance of neural nets with only a few complex neurons instead of many simple ones. A lot of application concepts arise from this idea: Kohonen himself applied it to speech recognition, but the project did not overcome much more than the recognition of the numerals one to ten at that time. A more promising application for self-organizing maps is process control and process monitoring. Several proposals were made which concern parameter classification of semiconductor technologies, design of integrated circuits, and control of chemical processes. Self-organizing maps were applied to robotics. The neural concept was introduced into electric power systems. At Dortmund we are working on a system which has to monitor the quality and the reliability of gears and electrical motors in equipment installed in coal mines. The results are promising and the probability to apply the system in the field is very high. A special feature of the system is that linguistic rules which are embedded in a fuzzy controller analyze the data of the self-organizing map in regard to life expectation of the gears. It seems that the fuzzy technique will introduce the technology of neural networks in a tandem mode. These technologies together with the genetic algorithms start to form the attractive field of computational intelligence.
Goser, Karl↗
VLSI Processor For Vector Quantization
Pixel intensities in each kernel compared simultaneously with all code vectors. Prototype high-performance, low-power, very-large-scale integrated (VLSI) circuit designed to perform compression of image data by vector-quantization method. Contains relatively simple analog computational cells operating on direct or buffered outputs of photodetectors grouped into blocks in imaging array, yielding vector-quantization code word for each such block in sequence. Scheme exploits parallel-processing nature of vector-quantization architecture, with consequent increase in speed.
Tawel, Raoul↗
Sequence information signal processor for local and global string comparisons
A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.
Peterson, John C.↗
Circuit for Communication Over Power Lines
Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.
Krasowski, Michael J.↗
ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays
The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.
Vasile, Stefan↗
Challenges Regarding IP Core Functional Reliability
For many years, intellectual property (IP) cores have been incorporated into field programmable gate array (FPGA) and application specific integrated circuit (ASIC) design flows. However, the usage of large complex IP cores were limited within products that required a high level of reliability. This is no longer the case. IP core insertion has become mainstream including their use in highly reliable products. Due to limited visibility and control, challenges exist when using IP cores and subsequently compromise product reliability. We discuss challenges and suggest potential solutions to critical application IP insertion.
IP cores↗