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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Total-dose radiation effects data for semiconductor devices. 1985 supplement. Volume 2, part A

Steady-state, total-dose radiation test data, are provided in graphic format for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. This volume provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done using the JPL or Boeing electron accelerator (Dynamitron) which provides a steady-state 2.5 MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose.

Martin, K. E.↗
NASA NTRS1986

Total-dose radiation effects data for semiconductor devices. 1985 Supplement. Volume 2, part B

Steady-state, total-dose radiation test data are provided in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 (Parts A and B) provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done steady-state 2.5-MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose. All data were generated in support of NASA space programs by the JPL Radiation Effects and Testing Group (514).

Martin, K. E.↗
NASA NTRS2005

MSAP Hardware Verification: Testing Multi-Mission System Architecture Platform Hardware Using Simulation and Bench Test Equipment

The Multi-Mission System Architecture Platform (MSAP) project aims to develop a system of hardware and software that will provide the core functionality necessary in many JPL missions and can be tailored to accommodate mission-specific requirements. The MSAP flight hardware is being developed in the Verilog hardware description language, allowing developers to simulate their design before releasing it to a field programmable gate array (FPGA). FPGAs can be updated in a matter of minutes, drastically reducing the time and expense required to produce traditional application-specific integrated circuits. Bench test equipment connected to the FPGAs can then probe and run Tcl scripts on the hardware. The Verilog and Tcl code can be reused or modified with each design. These steps are effective in confirming that the design operates according specifications.

Crossin, Kent R.↗
NASA NTRS2004

Dynamic SDRAM SEFI Detection and Recovery Test Results

Single event functionality interrupt (SEFI) results are presented for Hynix SDRAMS. The SEFI response threshold is below LET 9.9 Mev-cm(exp 2)/mg and the saturated cross section is 6 x 10(exp -5)cm(exp 2). Dynamic SEFI identification was made, and in-situ recovery restored functionality. Verification results of the identification algorithm are presented. An observed high current radiation response is also presented.

radiation effects↗
NASA NTRS1977

Integrated circuit process and design rule evaluation techniques

A technique is described for determining the applicability of a particular process for the fabrication of large-scale integrated (LSI) circuits. Test arrays were developed to isolate various critical processing steps in a fabrication sequence and a statistical evaluation of these steps was carried out that related yield or success in achieving a desired result to the number of times the results were attempted. It was found that, in general, yield is a sensitive function of physical dimensions as is the packing density of a particular array. It is, therefore, possible to generate an optimum set of physical dimensions or design rules that maximize the expected number of working circuits on a wafer.

Ipri, A. C.↗
NASA NTRS1981

Automatic arc welding of propulsion system tubing in close proximity to sensitive electronic devices

The planned final assembly of the Galileo spacecraft propulsion system tubing, which involves welding in close proximity to sensitive electronics, raised significant concerns about the effects of electromagnetic coupling of weld energy on CMOS and other sensitive integrated circuits. A test program was established to assess the potential of an orbital arc welder and an RF-induction brazing machine to damage sensitive electronic equipment. Test parameters were varied to assess the effectiveness of typical transient suppression practices such as grounding, bonding, and shielding. A technique was developed to calibrate the hazard levels at the victim-circuit location; this technique is described along with the results and conclusions of the test program.

Lumsden, J. M.↗
NASA NTRS1991

Cross-Quint-Bridge Resistor

Integrated-circuit conductive test pattern intended to provide data on effects of design widths and design spacings upon actual widths of conductive lines. Provides for electrical measurements both on lines of unknown width and on features having known dimensions. Data from measurements on five bridges used to determine four parameters of mathematical model describing system. In principle, pattern determines effects of width and spacing and interaction between them.

Hannaman, David J.↗
NASA NTRS1987

VLSI-Chip Tester

Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

Deutsch, Leslie J.↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗
NASA NTRS2019

Room Temperature Radiation Testing of a 500 °C Durable 4H-SiC JFET Integrated Circuit Technology

Total ionizing dose (TID) and single-event effect (SEE) room-temperature radiation test results are presented for developmental prototype 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) that have demonstrated prolonged operation in extremely high-temperature (500 °C) environments. The devices tested demonstrated over 7 Mrad(Si) TID tolerance and no destructive SEE susceptibility.

Lauenstein, Jean-Marie↗
NASA NTRS1985

Single event upset immune integrated circuits for Project Galileo

Tests showed that bipolar chips in the attitude control computer of the Galileo spacecraft would likely cause catastrophic mission failure due to single particle upset. This paper describes the design and testing of CMOS replacements which are speed compatible with the bipolar parts and are immune to upset by 165-MeV krypton ions.

Giddings, A. E.↗
NASA NTRS1985

Total-dose radiation effects data for semiconductor devices: 1985 supplement, volume 1

Steady-state, total-dose radiation test data are provided, in graphic format, for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. The document is in two volumes: Volume 1 provides data on diodes, bipolar transistors, field effect transistors, and miscellaneous semiconductor types, and Volume 2 provides total-dose radiation test data on integrated circuits. Volume 1 of this 1985 Supplement contains new total-dose radiation test data generated since the August 1, 1981 release date of the original Volume 1. Publication of Volume 2 of the 1985 Supplement will follow that of Volume 1 by approximately three months.

Martin, K. E.↗