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At least 73 records · Page 4

FPGA Coprocessor Design for an Onboard Multi-Angle Spectro-Polarimetric Imager

A multi-angle spectro-polarimetric imager (MSPI) is an advanced camera system currently under development at JPL for possible future consideration on a satellite-based Aerosol-Cloud-Environ - ment (ACE) interaction study. The light in the optical system is subjected to a complex modulation designed to make the overall system robust against many instrumental artifacts that have plagued such measurements in the past. This scheme involves two photoelastic modulators that are beating in a carefully selected pattern against each other. In order to properly sample this modulation pattern, each of the proposed nine cameras in the system needs to read out its imager array about 1,000 times per second. The onboard processing required to compress this data involves least-squares fits (LSFs) of Bessel functions to data from every pixel in realtime, thus requiring an onboard computing system with advanced data processing capabilities in excess of those commonly available for space flight. As a potential solution to meet the MSPI onboard processing requirements, an LSF algorithm was developed on the Xilinx Virtex-4FX60 field programmable gate array (FPGA). In addition to configurable hardware capability, this FPGA includes Power -PC405 microprocessors, which together enable a combination hardware/ software processing system. A laboratory demonstration was carried out based on a hardware/ software co-designed processing architecture that includes hardware-based data collection and least-squares fitting (computationally), and softwarebased transcendental function computation (algorithmically complex) on the FPGA. Initial results showed that these calculations can be handled using a combination of the Virtex- 4TM Power-PC core and the hardware fabric.

Pingree, Paula J.

Optimization of Selected Remote Sensing Algorithms for Embedded NVIDIA Kepler GPU Architecture

This paper evaluates the potential of embedded Graphic Processing Units (GPUs) in Nvidia's Tegra K1 (based on Kepler (TM) hardware) for onboard processing. The performance is compared to a general purpose multi-core CPU (Central Processing Unit) and a fully-fledged GPU accelerator. This study uses two algorithms: Wavelet Spectral Dimension Reduction of Hyperspectral Imagery and Automated Cloud-Cover Assessment (ACCA) Algorithm. Tegra K1 achieved 51 for the ACCA algorithm and 20 for the dimension reduction algorithm, as compared to the performance of the high-end 8-core server Intel Xeon CPU with 13.5 times higher power consumption.

data reduction

Prototype and Metrics for Data Processing Chain Components of IPM

This presentation lays out the evolution of the Intelligent Payload Module (IPM) vision given that the HyspIRI mission has been delayed. It shows that there has been a focus on airborne vehcile and unmanned aerial systems to further develop the IPM functionality. This of course does not preclude use of the IPM for space missions but provides alternate paths to continue the concept of improved onboard processing for low latency users of science data products.

Onboard Processing

Prototype and Metrics for Data Processing Chain Components of IPM

This presentation lays out the evolution of the Intelligent Payload Module (IPM) vision given that the HyspIRI mission has been delayed. It shows that there has been a focus on airborne vehcile and unmanned aerial systems to further develop the IPM functionality. This of course does not preclude use of the IPM for space missions but provides alternate paths to continue the concept of improved onboard processing for low latency users of science data products.

SpaceCube 2.0: An Advanced Hybrid Onboard Data Processor

The SpaceCube 2.0 is a compact, high performance, low-power onboard processing system that takes advantage of cutting-edge hybrid (CPU/FPGA/DSP) processing elements. The SpaceCube 2.0 design concept includes two commercial Virtex-5 field-programmable gate array (FPGA) parts protected by gradiation hardened by software" technology, and possesses exceptional size, weight, and power characteristics [5x5x7 in., 3.5 lb (approximately equal to 12.7 x 12.7 x 17.8 cm, 1.6 kg) 5-25 W, depending on the application fs required clock rate]. The two Virtex-5 FPGA parts are implemented in a unique back-toback configuration to maximize data transfer and computing performance. Draft computing power specifications for the SpaceCube 2.0 unit include four PowerPC 440s (1100 DMIPS each), 500+ DSP48Es (2x580 GMACS), 100+ LVDS high-speed serial I/Os (1.25 Gbps each), and 2x190 GFLOPS single-precision (65 GFLOPS double-precision) floating point performance. The SpaceCube 2.0 includes PROM memory for CPU boot, health and safety, and basic command and telemetry functionality; RAM memory for program execution; and FLASH/EEPROM memory to store algorithms and application code for the CPU, FPGA, and DSP processing elements. Program execution can be reconfigured in real time and algorithms can be updated, modified, and/or replaced at any point during the mission. Gigabit Ethernet, Spacewire, SATA and highspeed LVDS serial/parallel I/O channels are available for instrument/sensor data ingest, and mission-unique instrument interfaces can be accommodated using a compact PCI (cPCI) expansion card interface. The SpaceCube 2.0 can be utilized in NASA Earth Science, Helio/Astrophysics and Exploration missions, and Department of Defense satellites for onboard data processing. It can also be used in commercial communication and mapping satellites.

Lin, Michael

On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices.

Shyy, Dong-Jye

High-Performance Spaceflight Computing (HPSC) Project Overview

The High Performance Spaceflight Computing (HPSC) multi-core processor Chiplet will provide a nearly two orders-of-magnitude improvement above the current state of the art for spaceflight processors, while also providing an unprecedented flexibility to tailor performance, power consumption, and fault tolerance to meet widely varying mission needs. These advancements will provide game changing improvements in computing performance, power efficiency, and flexibility, which will significantly improve the onboard processing capabilities of future NASA and Air Force space missions. HPSC is funded by NASA's Space Technology Mission Directorate (STMD), Science Mission Directorate (SMD), and the United States Air Force. The HPSC project is managed by Jet Propulsion Laboratory, and the HPSC contract is managed by NASA Goddard Space Flight Center (GSFC). Within the HPSC project, Boeing is under contract to NASA to develop prototype Chiplets, system software, and evaluation boards. As another development within the project, NASA Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL) are developing middleware that will simplify application development for HPSC-based onboard processors.

multi-core processor

Optimization of Selected Remote Sensing Algorithms for Embedded NVIDIA Kepler GPU Architecture

This paper evaluates the potential of embedded Graphic Processing Units in the Nvidias Tegra K1 for onboard processing. The performance is compared to a general purpose multi-core CPU and full fledge GPU accelerator. This study uses two algorithms: Wavelet Spectral Dimension Reduction of Hyperspectral Imagery and Automated Cloud-Cover Assessment (ACCA) Algorithm. Tegra K1 achieved 51 for ACCA algorithm and 20 for the dimension reduction algorithm, as compared to the performance of the high-end 8-core server Intel Xeon CPU with 13.5 times higher power consumption.

Riha, Lubomir

Precomputing Process Noise Covariance for Onboard Sequential Filters

Process noise is often used in estimation filters to account for unmodeled and mismodeled accelerations in the dynamics. The process noise covariance acts to inflate the state covariance over propagation intervals, increasing the uncertainty in the state. In scenarios where the acceleration errors change significantly over time, the standard process noise covariance approach can fail to provide effective representation of the state and its uncertainty. Consider covariance analysis techniques provide a method to precompute a process noise covariance profile along a reference trajectory using known model parameter uncertainties. The process noise covariance profile allows significantly improved state estimation and uncertainty representation over the traditional formulation. As a result, estimation performance on par with the consider filter is achieved for trajectories near the reference trajectory without the additional computational cost of the consider filter. The new formulation also has the potential to significantly reduce the trial-and-error tuning currently required of navigation analysts. A linear estimation problem as described in several previous consider covariance analysis studies is used to demonstrate the effectiveness of the precomputed process noise covariance, as well as a nonlinear descent scenario at the asteroid Bennu with optical navigation.

onboard

An Ethics-Based Review of Generative Artificial Intelligence: Assuring Responsible Use (Version 1.0)

The rapid expansion of generative artificial intelligence (GenAI) has generated excitement regarding its potential benefits and concern over its ethical implications. Governments, corporations, and standards organizations have described ethical principles to direct GenAI's development and use; however, practical guidance for implementing these principles is limited. Addressing this gap is critical, especially considering the array of risks associated with GenAI, such as legal liabilities, privacy concerns, security threats, and potential misuse. Robust policies and procedures are critical to support responsible deployment of GenAI. This report examines Pacific Northwest National Laboratory (PNNL)’s approach to promoting responsible GenAI use. Proposed initiatives include developing policies based on ethical principles, creating a governance process to review projects relative to those principles, and implementing onboarding processes for training staff. The governance framework described in this report adapts the structure and principles of Institutional Review Boards (IRBs), traditionally used in human subjects research, for GenAI ethical review, providing oversight. Ethical principles guiding responsible GenAI usage include transparency and accountability, privacy, fairness, safety, security, and validity and reliability. To operationalize these principles, we propose forming a GenAI Assurance Council (GAC) that mirrors the IRB's structure. The GAC will evaluate GenAI projects across privacy, accountability, transparency, safety, security, fairness, and validity dimensions. Complementing policy and governance is AI literacy training to support staff understanding of GenAI's ethical implications. An initial training effort for AI Incubator Chat—a GenAI tool deployed at PNNL—showed promising results, underscoring the importance of clear guidelines and user accountability. Collaborative efforts and the dissemination of best practices are also discussed. The proposed GAC model and AI literacy training provide a blueprint for establishing ethical GenAI use and governance, offering practical tools to bridge the gap between ethical principles and real-world applications. The responsible integration of GenAI at PNNL entails a multifaceted approach involving policy development, ethical governance, and AI literacy training. The positive initial feedback and collaborative opportunities position PNNL to lead by example in GenAI's responsible use, reflecting a proactive stance in addressing the ethical, legal, and societal challenges associated with this emerging technology. PNNL's systematic and ethical approach to GenAI offers a model for other institutions to emulate, promoting safe and responsible technological advancements in the AI domain.

97 MATHEMATICS AND COMPUTING

A partial oxidation staging concept for gas turbines using broadened specification fuels

A concept is described for using a very fuel-rich partial oxidation process as the first stage of a two-stage combustion system for onboard processing of broadened specification fuels to improve their combustion characteristics. Results of an initial step in the experimental verification of the concept are presented, where the basic benefits of H2 enrichment are shown to provide extended lean-combustion limits and permit simultaneous achievement of ultralow levels of NOx, CO, and HC emissions. The H2 required to obtain these results is within the range available from a partial oxidation precombustion stage. Operation of a catalytic partial oxidation reactor using a conventional aviation turbine fuel (JP5) and an unconventional fuel (blend of JP5/xylene) is shown to produce a 'fuel gas' stream with near-theoretical equilibrium H2 content. However, a number of design considerations indicate that the precombustion stage should be incorporated as a thermal reaction.

Clayton, R. M.

Using a Multicore Processor for Rover Autonomous Science

Multicore processing promises to be a critical component of future spacecraft. It provides immense increases in onboard processing power and provides an environment for directly supporting fault-tolerant computing. This paper discusses using a state-of-the-art multicore processor to efficiently perform image analysis onboard a Mars rover in support of autonomous science activities.

Mars

An innovative on-board processor for lightsats

The Applied Physics Laboratory (APL) has developed a flightworthy custom microprocessor that increases capability and reduces development costs of lightsat science instruments. This device, called the FRISC (FORTH Reduced Instruction Set Computer), directly executes the high-level language called FORTH, which is ideally suited to the multitasking control and data processing environment of a spaceborne instrument processor. The FRISC will be flown as the onboard processor in the Magnetic Field Experiment on the Freja satllite. APL has achieved a significant increase in onboard processing capability with no increase in cost when compared to the magnetometer instrument on Freja's predecessor, the Viking satellite.

Henshaw, R. M.

Science Planning for the NASA Mars Reconnaissance Orbiter Mission

The Mars Reconnaissance Orbiter (MRO), launched on August 12, 2005, carries six science instruments, each with unique requirements for repetitive global monitoring, regional or global survey mapping, and/or targeted observations of Mars. Some prefer nadir-only observations, while other instruments require many off-nadir observations (especially for stereo viewing). Because the operations requirements are often incompatible, an interactive science planning process has been developed. This process is more complex than in some recent NASA Mars missions, but less complex (and more repetitive) than processes used by many large planetary missions. It takes full advantage of MRO's novel onboard processing capabilities, and uses simple electronic interactions between geographically distributed teams. This paper describes the process used during MRO's Primary Science Phase (PSP) to plan both interactive and non-interactive observations of Mars, and what has already been learned in the tests and rehearsals preparing for PSP.

planning

Automated Planning of Science Products Based on Nadir Overflights and Alerts for Onboard and Ground Processing

A set of automated planning algorithms is the current operations baseline approach for the Intelligent Payload Module (IPM) of the proposed Hyper spectral Infrared Imager (HyspIRI) mission. For this operations concept, there are only local (e.g. non-depletable) operations constraints, such as real-time downlink and onboard memory, and the forward sweeping algorithm is optimal for determining which science products should be generated onboard and on ground based on geographical overflights, science priorities, alerts, requests, and onboard and ground processing constraints. This automated planning approach was developed for the HyspIRI IPM concept. The HyspIRI IPM is proposed to use an X-band Direct Broadcast (DB) capability that would enable data to be delivered to ground stations virtually as it is acquired. However, the HyspIRI VSWIR and TIR instruments will produce approximately 1 Gbps data, while the DB capability is 15 Mbps for a approx. =60X oversubscription. In order to address this mismatch, this innovation determines which data to downlink based on both the type of surface the spacecraft is overflying, and the onboard processing of data to detect events. For example, when the spacecraft is overflying Polar Regions, it might downlink a snow/ice product. Additionally, the onboard software will search for thermal signatures indicative of a volcanic event or wild fire and downlink summary information (extent, spectra) when detected, thereby reducing data volume. The planning system described above automatically generated the IPM mission plan based on requested products, the overflight regions, and available resources.

Chien, Steve A.

Onboard configuration and operation of the TDRSS onboard navigation system (TONS)

This paper presents an overview of onboard navigation via TDRSS for both the EP/EUVE (Explorer Platform/Extreme Ultraviolet Explorer) experiment and for future users of TONS. System goals and objectives are discussed, and the operations concept for the three stages of TONS development is presented. A description is given of the first stage of the TONS development, the experiment implementation on EP, including the hardware characteristics, signal acquisition process, onboard data acquisition, and ground data processing in the flight emulation environment of the TONS Ground Support System (TGSS). Evaluation of the experiment implementation is presented and improvements described in terms of the second development stage, a full TONS I system, which uses Doppler data derived from scheduled forward-link S-band services to provide onboard orbit and frequency determination. A method for onboard time maintenance commensurate with TONS I is also presented. TONS II, the third stage, will use Doppler and pseudorange data derived from a continuous, nonscheduled forward-link S-band beacon service to provide onboard orbit, time, and frequency determination.

Gramling, Cheryl J.