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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Power Conversion Systems Enabled by SiC BiDFET Device

The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. Furthermore, the matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac-ac and ac dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

42 ENGINEERING↗
DOE OSTI2023

PV Inverter Systems Enabled by Monolithically Integrated SiC based Four Quadrant Power Switch (4-QPS) [BiDFET]

The purpose of this project was to develop a new breed of Power Conversion Systems (PCS) for PV integration that is enabled by the newly developed 4-Quadrant Single Die SiC Power Semiconductor Switches (4-QPS) or also referred to as “Bidirectional FET (BIDFET)”. This work includes semiconductor die development, advanced packaging, converter design, development, and testing of 4-QPS enabled hardware prototypes at 1 kW (for single phase residential application) and 10 kW (for three phase commercial application). The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

An Organic, Direct Bonded Copper, Multi-Layered, Ultra-Low Inductance Package for High-Power UWBG MOSFETs

The most common metalized substrates used in high-power switching packages consist of a ceramic layer such as Aluminum Nitride (AlN) sandwiched between two copper layers. Ceramic substrates are used because it has the key characteristic of having high dielectric strength while being thermally conductive. A large drawback to ceramic substrates is that they do not allow for a multi-layered circuit design. By replacing the traditional ceramic substrate with organic direct bonded copper (ODBC) we can open a wide range of possibilities when it comes to power module layout such as multi-layered circuits and double-sided cooling. Both benefits are critical while packaging high-performance Gallium Oxide (Ga2O3) MOSFETs. Because of Ga2O3's relatively poor thermal conductivity, a double-sided cooled package becomes necessary. Therefore, the use of ODBC provides the flexibility to fabricate copper traces carrying much higher currents, and by creating a multi-layered package, we can drastically reduce the parasitic inductance inside the power module. Achieving lower parasitic inductance is critical for an ultra-fast Ga2O3 package to avoid excessive voltage overshoot and ringing. Using ODBC, we have designed novel packages capable of handling the challenges presented by fast Ga2O3 switching. Using multi-physics modeling software, we can validate our design before building the prototype. Due to the simple process parameters needed to work with ODBC, we can rapidly create prototypes without using external vendors. This flexibility allows us to quickly design, build, and validate highly complex switching power modules to accommodate next generation, Ga2O3 switching devices.

ADVANCED PROPULSION SYSTEMS,ENGINEERING↗
DOE OSTI2021

Electric-Drive Vehicle Power Electronics Thermal Management: Current Status, Challenges, and Future Directions

Effective thermal management of traction-drive power electronics is critical to the advancement of electric-drive vehicles and is necessary for increasing power density and improving reliability. Replacing traditional silicon devices with more efficient, higher temperature, higher voltage, and higher frequency wide-bandgap (WBG) devices will enable increased power density but will result in higher device heat fluxes. Compact packaging of high-temperature WBG devices near low-temperature-rated components creates thermal management challenges that need to be addressed for future power-dense systems. This paper summarizes the thermal performance of on-road automotive power electronics thermal management systems and provides thermal performance and pumping-power metrics for select vehicles. Thermal analyses reveal that the package/conduction resistance dominates the total thermal resistance (for existing automotive systems). We model advanced packaging concepts and compare the results with existing packaging designs to quantify their thermal performance enhancements. Double-side-cooled configurations that do not use thermal interface materials are package concepts predicted to provide a low junction-to-fluid thermal resistance (compared to current packages). Dielectric-fluid-cooled concepts enable a redesign of the package to reduce the package resistance, can be implemented in single- and two-phase cooling approaches, and allow for cooling of passive components (e.g., capacitors) and bus bars.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2023

Cost analysis of distributed storage in AC and DC microgrids

Building and microgrid designs with highly-distributed electrical storage have potential advantages over today's conventional topologies with centralized storage. Herein this paper studies the capital cost benefits of several residential behind-the-meter distributed-storage topologies, including AC and DC versions of systems with load-packaged batteries and resilient sub-networks. The study begins by defining the block configuration of each topology. This work then develops a model for the cost of the power electronics necessary to interface with the storage elements. Finally, the analysis develops a model for the total cost of each storage topology, incorporating the installation and soft costs. The results suggest that while the cost of power electronics is lower in centralized topologies, the total cost is lower for distributed storage due to the avoided costs of installation and permitting. This paper also explores the benefits of load-packaged batteries for savings in electrical infrastructure.

25 ENERGY STORAGE↗
DOE OSTI2020

Guest Editorial: Special Issue on InterPACK 2019 - Part 1

This is a collection of papers drawn from the 2019 ASME InterPACK Conference. The content spans the areas of heterogeneous integration, servers, flexible and wearable electronics, photonics, power electronics, energy storage, and autonomous and electric vehicles.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Power Electronics Thermal Management

The 2017 Electrical and Electronics Technical Team Roadmap [11] proposes aggressive research and development targets aimed at improving power electronics technology to enable the mass-market penetration of electric-drive vehicles. Achieving these aggressive targets will require a decrease in cost (year 2025 cost target: $2.70/kW) and an increase in power density (year 2025 power density target: 100 kW/L) as compared with current on-road technology. Replacing traditional silicon device-based components with more efficient and higher-temperature wide-bandgap (WBG) semiconductor device-based components will enable increased power density. However, meeting the power density target will also require innovative thermal management solutions to increase the heat fluxes dissipated and allow for compact electronics packaging. This project evaluates, designs, and develops thermal management strategies that use dielectric fluid (single-phase heat transfer) as coolants.

ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2020

Runtime power allocation approach for GAMESS hybrid CPU‐GPU implementation

Summary To improve power consumption of applications at the runtime, modern processors provide frequency scaling capabilities, which along with workload optimization, are also available on GPU accelerators. In this work, a runtime strategy is proposed to distribute a given power allocation among the host components and the GPU according to the current application performance and power usage, such that GPU execution is prioritized over CPU for power allocation to maximize application performance. Next, the strategy is tailored to an application, a quantum‐chemistry package GAMESS for ab initio electronic structure calculations. Specifically, GAMESS hybrid CPU–GPU implementation as provided in the Libcchem library is considered. Experiments, performed on a 28‐core node with a Kepler GPU, resulted in performance gains of up to 50% under the proposed strategy and the largest power allocation considered here as compared with the scenario when this allocation was equally distributed among the computing‐platform components.

Sundriyal, Vaibhav↗
DOE OSTI2024

Heterogeneous Integration Technologies for High-temperature, High-density, Low-profile Power Modules of Wide Bandgap Devices in Electric Drive Applications (Final Technical Report)

The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2026

The Heterogeneous Integration of Electronic Components

Heterogeneous integration (HI) of electronics components is broadly recognized as a powerful and crucial enabler for the continued growth of computing and communication. From 2010 onwards, the value of HI is increasingly visible in the advanced packaging used in artificial intelligence, high-performance computing, smartphones and communications product implementations. In this Perspective, we argue that HI is crucial to semiconductors and more broadly to the continued evolution of computing and communications. We use leading-edge advanced packaging examples to represent the value, advancements and opportunities for HI. To succeed, it is critical to develop comprehensive HI roadmaps that inform collaborations across the design, manufacturing and reliability spectrum between systems architects, packaging and semiconductor technologists to common goals. Although this article does not provide a full roadmap, we instead detail additional parameters for artificial intelligence, smartphone and other cellular communication devices, and their constituent building blocks including interconnects, power electronics, photonics, thermal management, reliability, modelling and co-design, to foster greater collaboration opportunities among academia, research laboratories and industry.

42 ENGINEERING↗
DOE OSTI2020

Power Electronics Thermal Management

This project conducts research to develop new power electronics thermal management technologies to increase power density, enable high WBG temperature operation, and decrease cost. One of the main challenges to achieving high power densities is associated with packaging of high-temperature (250°C) WBG devices near lower-temperature-rated components (e.g., electrical boards and capacitors). Additionally, the high junction temperatures of the WBG devices will result in large temperature gradients through the power module layers that will present reliability challenges and require higher-temperature substrates and bonding materials.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

NWChem: Past, present, and future

Specialized computational chemistry packages have permanently reshaped the landscape of chemical sciences by providing tools to support and guide the experimental effort and for prediction of chemical and materials properties. In this regard, a special role has been played by electronic structure packages where complex chemical and materials processes can be modeled using first-principle-driven methodologies. Over the last few decades, the rapid development of computing technologies and a tremendous increase in computational power has offered a unique chance to study complex chemical transformations using sophisticated and predictive many-body techniques to describe correlated behavior of electrons in molecular and condensed phase systems at different levels of theory. In enabling these simulations, a critical role has been played by novel parallel algorithms capable of taking advantage of computational resources to address polynomial scaling of electronic structure methods. NWChem was among the first electronic structure codes that focused on delivering scalable performance for electronic structure simulations. Herein, we briefly review the NWChem suite of computational codes including its history, design principles, parallel tools, current capabilities, outreach and outlook.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Power Electronics Thermal Management

This project conducts research to develop new power electronics thermal management technologies to increase power density, enable high WBG temperature operation, and decrease cost. One of the main challenges to achieving high power densities is associated with packaging of high-temperature (up to 250 degrees C) WBG devices near lower-temperature-rated components (e.g., electrical boards and capacitors). Additionally, the high junction temperatures of the WBG devices will result in large temperature gradients through the power module layers, which will present reliability challenges and require higher-temperature substrates and bonding materials.

ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2020

BEEAM (Building Electrical Efficiency Analysis Model) [SWR-20-107]

Modern high-performance buildings exhibit an increasing number of building loads that use direct current (DC) electricity internally, rather than alternating current (AC), due to the advent of low-cost computing and advanced power electronics. Powering DC devices from the AC grid requires AC/DC power conversion, which introduces energy losses and reduces efficiency. As DC loads proliferate, the cumulative wasted energy associated with hundreds of millions of AC/DC converters has become one of the broadest energy savings opportunities in buildings. DC power distribution systems have been proposed as an elegant and transformative solution to the problem of DC devices. In a DC distribution system, the building's wires carry DC electricity, rather than AC; and a few centralized, highly efficient AC/DC converters replace the many smaller, less efficient converters that serve individual DC loads. Unfortunately, the trade-offs associated with DC distribution systems are not well understood. Reported energy savings associated with DC power distribution differ widely and have not been well validated. The Building Electrical Efficiency Analysis Model (BEEAM) is a Modelica library that simulates the efficiency of building electrical distribution systems using harmonic power flow. BEEAM can model a wide variety of building distribution topologies, including three-phase AC, single-phase AC, unipolar DC, bipolar DC, and hybrid networks under both balanced and unbalanced load conditions. BEEAM accurately models power electronic converter losses, provides granular estimates of losses throughout the distribution system, and properly models efficiency at part load conditions. Users can package BEEAM within a functional mockup unit (FMU), enabling co-simulation with other modeling platform, such as EnergyPlus. In summary, BEEAM provides a tool suite for fair and accurate comparison of the efficiency of building electrical distribution systems, including AC, DC, and hybrid systems.

Frank, Stephen↗
DOE OSTI2026

Power Electronic Development Challenges for High Power Density Integrated Electric Drive Applications

The ever-increasing demand for compact, efficient, and high-performance traction drive systems for transportation applications has accelerated the development of integrated electric drives. In these systems, the electric machine and inverter are integrated within a single housing, offering significant advantages in electrical performance, volume, weight, cost, and overall system efficiency. Despite these benefits, such high levels of integration introduce a new set of challenges, particularly in power electronic design and component selection. This article presents an in-depth investigation of a highly integrated electric drive architecture with an internal stator-mounted inverter, highlighting key design considerations and trade-offs aimed exclusively at maximizing system power density.Based on a comprehensive review of the literature, the power density of a voltage-source-inverter-driven electric drive is primarily governed by the volumetric contributions of the power modules, heat sinks, and DC-link capacitors. Accordingly, this work focuses on the optimization of these three critical components to enhance the inverter's overall power density. The proposed design achieves a power density of 100 kW/L, demonstrating the effectiveness of the presented approach for next-generation integrated electric drive systems.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

2025 InterPACK: Thermal Management and Reliability Aspects

The presentation will provide an overview of automotive power electronics and electric machines thermal management systems that are typical for light-duty vehicles. Unique thermal and environmental aspects related to medium and heavy-duty vehicle applications will then be discussed. Finally, advanced thermal management and packaging technologies that could be evaluated and used in this project will be described.

33 ADVANCED PROPULSION SYSTEMS↗