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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 721 records · Page 40
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Comparison of phase modulation systems

Comparison of the energy to noise ratio necessary to obtain a given modulation bit error probability has indicated that three-phase modulation is about 0.75 db superior to four-phase. It is shown that this apparent superiority results entirely from the greater bandwidth required by the three-phase system for the same bit transmission rate. Two further comparison criteria are proposed, which are based on the cut-off rate R sub 0 of the discrete channel created by the modulation system. For the criterion which constrains both the bandwidth and transmitted power, it is shown that four-phase modulation is always superior to three-phase modulation. The conclusion is that three-phase modulation offers no practical advantage over four-phase modulation.

Massey, J. L.↗
NASA NTRS1979

Radio frequency interference effects of continuous wave signals on telemetry data, part 2

The results of radio frequency interference tests and the derived telemetry bit SNR degradation model, which includes the telemetry data rate and the telemetry data power as independent variables for characterizing the continuous wave interference effects on telemetry data, are presented. The telemetry bit SNR degradation model was implemented in the second version of the Deep Space Interference Prediction software.

Low, P. W.↗
NASA NTRS1976

CMOS array design automation techniques

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lombardi, T.↗
NASA NTRS1979

Concurrent error detecting codes for arithmetic processors

A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes.

Lim, R. S.↗
NASA NTRS1979

Wideband optical storage

This paper has five purposes. First, to focus upon the key relationships that bound the technology choices for large, archival, digital storage devices; second, to identify the motivations for selecting the optical technology for a petabit-exabit level storage system (10 to the 15th to 10 to the 18th bits); third, to present a generic example and a specific implementation of a terabit-level optical storage device; fourth, to characterize the global design space constraints that will allow one to build a technology-limited optical store; and fifth, to sketch the outline of the BYTERON concept, a wideband 10 to the 16th to 10 to the 17th bit optical store concept and contrast its performance to that of an optical store that is in operation today

Heard, H. G.↗
NASA NTRS1978

A solid state data recorder for spacecraft telemetry applications

A solid state data recorder (SSDR) has been developed which offers a high-reliability alternative to tape recorders in many spacecraft telemetry applications. The storage medium used in this recorder was ferrimagnetic garnet films supporting nonvolatile magnetic bubble domains. The recorder was designed using modular construction consisting of a digital control unit, power supply, and two memory modules. A prototype SSDR has been fabricated which is designed for 100-million bits of storage but was populated with 128 chips for a 13-million bit capacity. Preliminary tests indicate satisfactory operation.

Stermer, R. L., Jr.↗
NASA NTRS1978

A versatile microprocessor-controlled hybrid receiver

A hybrid receiver has been designed for the Galileo Project. The receiver, located on the Galileo Orbiter, will autonomously acquire and track signals from the first atmospheric probe of Jupiter as well as demodulate, bit-synchronize, and buffer the telemetry data. The receiver has a conventional RF and LF front end but performs multiple functions digitally under firmware control. It will be a self-acquiring receiver that operates under a large frequency uncertainty; it can accommodate different modulation types, bit rates, and other parameter changes via reprogramming. A breadboard receiver and test set demonstrate a preliminary version of the sequential detection process and verify the hypothesis that a fading channel does not reduce the probability of detection.

Grant, T. L.↗
NASA NTRS1979

Algorithms for the Automated Power Systems Management

The system breadboard for the demonstration of Automated Power Systems Management (APSM) functions has been designed, fabricated, and is in the final stages of verification and testing. APSM functions fall into categories of fault detection and correction, commanding system and subsystem test and diagnoses, relay position monitoring, data acquisition and processing, and power management. All these functions are accomplished through software residing in 8-bit microprocessors dedicated to each group of Viking Orbiter power breadboard subassemblies and a 16-bit microprocessor serving as the central processor for the power system. This paper describes key monitoring, diagnostic, and control algorithms used in the APSM breadboard.

Moser, R. L.↗
NASA NTRS1981

Compressing TV-image data

Compressing technique calculates activity estimator for each segment of image line. Estimator is used in conjunction with allowable bits per line, N, to determine number of bits necessary to code each segment and which segments can tolerate truncation. Preprocessed line data are then passed to adaptive variable-length coder, which selects optimum transmission code. Method increases capacity of broadcast and cable television transmissions and helps reduce size of storage medium for video and digital audio recordings.

Hilbert, E. E.↗
NASA NTRS1980

Shuttle Ku-band and S-band communications implementation study

Various aspects of the shuttle orbiter S-band network communication system, the S-band payload communication system, and the Ku-band communication system are considered. A method is proposed for obtaining more accurate S-band antenna patterns of the actual shuttle orbiter vehicle during flight because the preliminary antenna patterns using mock-ups are not realistic that they do not include the effects of additional appendages such as wings and tail structures. The Ku-band communication system is discussed especially the TDRS antenna pointing accuracy with respect to the orbiter and the modifications required and resulting performance characteristics of the convolutionally encoded high data rate return link to maintain bit synchronizer lock on the ground. The TDRS user constraints on data bit clock jitter and data asymmetry on unbalanced QPSK with noisy phase references are included. The S-band payload communication system study is outlined including the advantages and experimental results of a peak regulator design built and evaluated by Axiomatrix for the bent-pipe link versus the existing RMS-type regulator. The nominal sweep rate for the deep-space transponder of 250 Hz/s, and effects of phase noise on the performance of a communication system are analyzed.

Dodds, J. G.↗
NASA NTRS1980

Space shuttle main engine digital controller

The controller provides responsive control of engine thrust and mixture ratio through the digital computer in the controller, updating the instructions to the engine control elements 50 times per second (every 20 milliseconds). Additionally, precise engine performance is achieved through closed loop control, utilizing 16 bit computation, 10 bit input/output resolution, and self calibrating analog-to-digital conversion. Engine reliability is enhanced by a dual redundant control system that allows normal operation after the first failure and a fail-safe shutdown after a second failure. The digital computer is programmable, allowing modification of engine control equations and constants by change of the stored program (software). The controller is packaged in a sealed, pressurized chassis with cooling provided by convection heat transfer through pin fins as part of the main chassis. The electronics are distributed on functional modules having special provisions for thermal and vibrational protection.

Mitchell, W. T.↗
NASA NTRS1980

The sensitivity of a very long baseline interferometer

The theoretical sensitivity of various methods of acquiring and processing interferometer data are compared. It is shown that for a fixed digital recording capacity one bit quantization of single sideband data filtered with a rectangular bandpass and sampled at the Nyquist rate yields the optimum signal to noise ratio. The losses which result from imperfect bandpass, poor image rejection, approximate methods of fringe rotation, fractional bit correction, and loss of quadrature are discussed. Also discussed is the use of the complex delay function as a maximum likelihood fringe estimator.

Rogers, A. E. E.↗
NASA NTRS1978

Report for simultaneous, multiple independently steered beam study for Airborne Electronically Steerable Phased Array (AESPA) program

Design concepts of an array for the formation of multiple, simultaneous, independently pointed beams for satellite communication links were investigated through tradeoffs of various approaches which were conceived as possible solutions to the problem. After the preferred approach was selected, a more detailed design was configured and is presented as a candidate system that should be given further consideration for development leading to a preliminary design. This array uses an attenuator and a phase shifter with every element. The aperture excitation necessary to form the four beams is calculated and then placed across the array using these devices. Pattern analysis was performed for two beam and four beam cases with numerous patterns being presented. Parameter evaluation shown includes pointing accuracy and beam shape, sidelobe characteristics, gain control, and beam normalization. It was demonstrated that a 4 bit phase shifter and a 6 bit, 30 dB attenuator were sufficient to achieve adequate pattern performances. The phase amplitude steered multibeam array offers the flexibility of 1 to 4 beams with an increase in gain of 6 dB if only one beam is selected.

Source record↗
NASA NTRS1980

Satellite communication performance evaluation: Computational techniques based on moments

Computational techniques that efficiently compute bit error probabilities when only moments of the various interference random variables are available are presented. The approach taken is a generalization of the well known Gauss-Quadrature rules used for numerically evaluating single or multiple integrals. In what follows, basic algorithms are developed. Some of its properties and generalizations are shown and its many potential applications are described. Some typical interference scenarios for which the results are particularly applicable include: intentional jamming, adjacent and cochannel interferences; radar pulses (RFI); multipath; and intersymbol interference. While the examples presented stress evaluation of bit error probilities in uncoded digital communication systems, the moment techniques can also be applied to the evaluation of other parameters, such as computational cutoff rate under both normal and mismatched receiver cases in coded systems. Another important application is the determination of the probability distributions of the output of a discrete time dynamical system. This type of model occurs widely in control systems, queueing systems, and synchronization systems (e.g., discrete phase locked loops).

Omura, J. K.↗
NASA NTRS1979

Programmable charge-coupled device /CCD/ correlator for pattern classification

The potential use of charge coupled device (CCD) programmable digital/analog correlators for multispectral data classification is discussed. CCD digital/analog correlator technology and the experimental evaluation of a 32-stage 4-bit test device are presented. The design of an IC for use in a multispectral classification system for 16 sensors and 8 bit accuracy is reviewed.

Mayer, D. J.↗
NASA NTRS1979

Cosmic ray-induced soft errors in static MOS memory cells

Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against cosmic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are in general agreement with previous spacecraft flight data.

Sivo, L. L.↗
NASA NTRS1980

A bubble memory module

A bubble memory module design providing flexibility for many user applications in spacecraft data recording is described. The memory module can be used with user-designed controllers with the memory organization determined by the application. Asynchronous data rates from zero to 1.33 Mbits/sec at minimum power are accomplished by using 8-chip memory cells with 100 K bit serial chips. The memory module is expandable from a 4 x 2 cell matrix to a 4 x 16 cell matrix corresponding to an expandable capacity of 6.55 M to 52.4 M bits. The module's design, utility in various memory systems, and user clocking scheme are described.

Hayes, P. J.↗
NASA NTRS1980

Comparison of three-phase modulation with two-phase and four-phase modulation

For a constant added noise density at high signal-to-noise ratios and for the same error rate, three-phase PSK requires about 0.75 dB less energy per bit than two-phase or four-phase PSK. However, at very low signal-to-noise ratios, three-phase PSK requires about 0.74 dB more energy per bit of channel capacity than two-phase or four-phase PSK.

Pierce, J. R.↗