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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 829 records · Page 46

Deep, Precise Etching in Semiconductors

Semiconductors made to accept precise etching after pretreatment. Combination of material destabilization and anisotropic etching permits formation of precise perpendicular-wall cavities in silicon wafers and other semiconductors. New technique extends capabilities of current micromachining technology to fabrication of submillimeter waveguide arrays and filters. Pre-etching process currently used to fabricate thin-walled arrays of submillimeter waveguides for use as dichroic bandpass filters. Possible applications include integration of sensor probes and processing of circuitry on same silicon chip.

Shlichta, P. J.↗

Highly Non-Linear Optical (NLO) organic crystals and films. Electrooptical organic materials

Devices employing nonlinear optics (NLO) hold great promise for important applications in integrated optics, optical information processing and telecommunications. Properly designed organics possess outstanding optical and electrooptical properties which will substantially advance many technologies including electrooptical switching, optical amplification for communications, and parallel processing for hybrid optical computers. A brief comparison of organic and inorganic materials is given.

Mcmanus, Samuel P.↗

CFD application to subsonic inlet airframe integration

The fluid dynamics of curved diffuser duct flows of military aircraft is discussed. Three-dimensional parabolized Navier-Stokes analysis, and experiment techniques are reviewed. Flow measurements and pressure distributions are shown. Velocity vectors, and the effects of vortex generators are considered.

Anderson, Bernhard H.↗

CFD application to supersonic/hypersonic inlet airframe integration

Supersonic external compression inlets are introduced, and the computational fluid dynamics (CFD) codes and tests needed to study flow associated with these inlets are outlined. Normal shock wave turbulent boundary layer interaction is discussed. Boundary layer control is considered. Glancing sidewall shock interaction is treated. The CFD validation of hypersonic inlet configurations is explained. Scramjet inlet modules are shown.

Benson, Thomas J.↗

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗

Study of a co-designed decision feedback equalizer, deinterleaver, and decoder

A technique that promises better quality data from band limited channels at lower received power in digital transmission systems is presented. Data transmission, in such systems often suffers from intersymbol interference (ISI) and noise. Two separate techniques, channel coding and equalization, have caused considerable advances in the state of communication systems and both concern themselves with removing the undesired effects of a communication channel. Equalizers mitigate the ISI whereas coding schemes are used to incorporate error-correction. In the past, most of the research in these two areas has been carried out separately. However, the individual techniques have strengths and weaknesses that are complementary in many applications: an integrated approach realizes gains in excess to that of a simple juxtaposition. Coding schemes have been successfully used in cascade with linear equalizers which in the absence of ISI provide excellent performance. However, when both ISI and the noise level are relatively high, nonlinear receivers like the decision feedback equalizer (DFE) perform better. The DFE has its drawbacks: it suffers from error propagation. The technique presented here takes advantage of interleaving to integrate the two approaches so that the error propagation in DFE can be reduced with the help of error correction provided by the decoder. The results of simulations carried out for both, binary, and non-binary, channels confirm that significant gain can be obtained by codesigning equalizer and decoder. Although, systems with time-invariant channels and simple DFE having linear filters were looked into, the technique is fairly general and can easily be modified for more sophisticated equalizers to obtain even larger gains.

Peile, Robert E.↗

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Smith, Edwyn D.↗

High-gain AlGaAs/GaAs double heterojunction Darlington phototransistors for optical neural networks

High-gain MOCVD-grown (metal-organic chemical vapor deposition) AlGaAs/GaAs/AlGaAs n-p-n double heterojunction bipolar transistors (DHBTs) and Darlington phototransistor pairs are provided for use in optical neural networks and other optoelectronic integrated circuit applications. The reduced base doping level used results in effective blockage of Zn out-diffusion, enabling a current gain of 500, higher than most previously reported values for Zn-diffused-base DHBTs. Darlington phototransitor pairs of this material can achieve a current gain of over 6000, which satisfies the gain requirement for optical neural network designs, which advantageously may employ neurons comprising the Darlington phototransistor pairs in series with a light source.

Kim, Jae H.↗

Test chips and ASIC qualification

A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

Buehler, M. G.↗

A three-dimensional approach for analysis of sidewall injector mixing and combustion

A three-dimensional (3-D) analytical approach to calculate the mixing and combustion efficiency along engine combustors that use sidewall fuel injectors is described. The analysis consists of three parts: (1) an empirical correlation for fuel penetration, (2) application of integral conservation laws following jet turning and pressure equilibration, and (3) an analytical solution for the simplified three-dimensional partial differential equations to describe the downstream mixing and combustion process. Numerical results are compared to some empirical and experimental work, and favorable agreements are shown. The importance of including anisotropic turbulence and three-dimensional effects are illustrated by comparison with data and other less comprehensive analyses. The analytical solution is suitable for rapid estimates of engine performance and parametric studies of combustor designs containing transverse or angled injector ports arranged in rows and/or columns.

Quan, Victor↗

Developing A Navier-Stokes Algorithm For Supercomputers

Report discusses development of algorithm for solution of Navier-Stokes equations of flow on parallel-processing supercomputers. Involves combination of prior techniques to form algorithm to compute flows in complicated three-dimensional configurations. Includes explicit finite-difference numerical-integration scheme applicable to flows represented by hierarchy of mathematical models ranging from Euler to full Navier-Stokes. Of interest to researchers looking for ways to structure problems for greater computational efficiency.

Swisshelm, Julie M.↗

A reconfigurable multicarrier demodulator architecture

An architecture based on parallel and pipline design approaches has been developed for the Frequency Division Multiple Access/Time Domain Multiplexed (FDMA/TDM) conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the Fast Fourier Transform (FFT). The demodulator consists of carrier, clock, and data recovery modules which are interactive. Progress on the design of the MultiCarrier Demodulator (MCD) using commercially available chips and Application Specific Integrated Circuits (ASIC) and simulation studies using Viewlogic software will be presented at the conference.

Kwatra, S. C.↗

Flexible High Speed Codec (FHSC)

The ongoing NASA/Harris Flexible High Speed Codec (FHSC) program is described. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K emitter coupled logic (ECL) which can be easily translated to an ECL gate array.

Segallis, G. P.↗

Programmable digital modem

The design of the Programmable Digital Modem (PDM) is outlined. The PDM will be capable of operating with numerous modulation techniques including: 2-, 4-, 8- and 16-ary phase shift keying (PSK), minimum shift keying (MSK), and 16-ary quadrature amplitude modulation (QAM), with spectral occupancy from 1.2x to 2x the data symbol rate. It will also be programmable for transmission rates ranging from 2.34 to 300 Mbit/s, where the maximum symbol rate is 75 Msymbol/s. Furthermore, these parameters will be executable in independent burst, dependent burst, or continuous mode. In dependent burst mode the carrier and clock oscillator sources are common from burst to burst. To achieve as broad a set of requirements as these, it is clear that the essential signal processing must be digital. In addition, to avoid hardware changes when the operational parameters are changed, a fixed interface to an analog intermediate frequency (IF) is necessary for transmission; and, common system level architectures are necessary for the modulator and demodulator. Lastly, to minimize size and power, as much of the design as possible will be implemented with application specific integrated circuit (ASIC) chips.

Poklemba, John J.↗

End-of-fabrication CMOS process monitor

A set of test 'modules' for verifying the quality of a complementary metal oxide semiconductor (CMOS) process at the end of the wafer fabrication is documented. By electrical testing of specific structures, over thirty parameters are collected characterizing interconnects, dielectrics, contacts, transistors, and inverters. Each test module contains a specification of its purpose, the layout of the test structure, the test procedures, the data reduction algorithms, and exemplary results obtained from 3-, 2-, or 1.6-micrometer CMOS/bulk processes. The document is intended to establish standard process qualification procedures for Application Specific Integrated Circuits (ASIC's).

Buehler, M. G.↗

Acquisition, representation and rule generation for procedural knowledge

Current research into the design and continuing development of a system for the acquisition of procedural knowledge, its representation in useful forms, and proposed methods for automated C Language Integrated Production System (CLIPS) rule generation is discussed. The Task Analysis and Rule Generation Tool (TARGET) is intended to permit experts, individually or collectively, to visually describe and refine procedural tasks. The system is designed to represent the acquired knowledge in the form of graphical objects with the capacity for generating production rules in CLIPS. The generated rules can then be integrated into applications such as NASA's Intelligent Computer Aided Training (ICAT) architecture. Also described are proposed methods for use in translating the graphical and intermediate knowledge representations into CLIPS rules.

Ortiz, Chris↗

An 8-PSK TDMA uplink modulation and coding system

The combination of 8-phase shift keying (8PSK) modulation and greater than 2 bits/sec/Hz drove the design of the Nyquist filter to one specified to have a rolloff factor of 0.2. This filter when built and tested was found to produce too much intersymbol interference and was abandoned for a design with a rolloff factor of 0.4. The preamble is limited to 100 bit periods of the uncoded bit period of 5 ns for a maximum preamble length of 500 ns or 40 8PSK symbol times at 12.5 ns per symbol. For 8PSK modulation, the required maximum degradation of 1 dB in -20 dB cochannel interference (CCI) drove the requirement for forward error correction coding. In this contract, the funding was not sufficient to develop the proposed codec so the codec was limited to a paper design during the preliminary design phase. The mechanization of the demodulator is digital, starting from the output of the analog to digital converters which quantize the outputs of the quadrature phase detectors. This approach is amenable to an application specific integrated circuit (ASIC) replacement in the next phase of development.

Ames, S. A.↗

The MARCOR GPS mobile data system

Market research revealed several key demands for an Automatic Vehicle Location (AVL) Global Positioning System (GPS) radio. The demands were for minimization of urban building blockage, easy programmability to minimize mobile data transmission costs, high accuracy for street map level coordination, interface capability with non-digital Specialized Mobile Radios (SMR), and a selling price close to that of alternatives such as Signposts and Loran-C. A team of experts was assembled to surmount these challenges and deliver a GPS radio for $500 to $1000, which operates at high accuracy in an urban environment and is plug-compatible with nearly all vehicle radios. Among the engineering and production breakthroughs described here are a unique Simultrac (Trademark) approach to satellite tracking, enabling up to eight GPS satellites to be used for position determination with a 2-channel receiver, and a receiver-in-a-microphone design. A powerful Application Specific Integrated Circuit (ASIC) allowed GPS to be brought within easy reach of millions of AVL users such as bus, taxi, and delivery vehicle fleets.

Rothblatt, Martin↗