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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1996

Silicon Carbide Epitaxial Films Studied by Atomic Force Microscopy

Silicon carbide (SiC) holds great potential as an electronic material because of its wide band gap energy, high breakdown electric field, thermal stability, and resistance to radiation damage. Possible aerospace applications of high-temperature, high-power, or high-radiation SiC electronic devices include sensors, control electronics, and power electronics that can operate at temperatures up to 600 C and beyond. Commercially available SiC devices now include blue light-emitting diodes (LED's) and high-voltage diodes for operation up to 350 C, with other devices under development. At present, morphological defects in epitaxially grown SiC films limit their use in device applications. Research geared toward reducing the number of structural inhomogeneities can benefit from an understanding of the type and nature of problems that cause defects. The Atomic Force Microscope (AFM) has proven to be a useful tool in characterizing defects present on the surface of SiC epitaxial films. The in-house High-Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center not only extended the dopant concentration range achievable in epitaxial SiC films, but it reduced the concentration of some types of defects. Advanced structural characterization using the AFM was warranted to identify the type and structure of the remaining film defects and morphological inhomogeneities. The AFM can give quantitative information on surface topography down to molecular scales. Acquired, in part, in support of the Advanced High Temperature Engine Materials Technology Program (HITEMP), the AFM had been used previously to detect partial fiber debonding in composite material cross sections. Atomic force microscopy examination of epitaxial SiC film surfaces revealed molecular-scale details of some unwanted surface features. Growth pits propagating from defects in the substrate, and hillocks due, presumably, to existing screw dislocations in the substrates, were imaged. Away from local defects, step bunching was observed to yield step heights of hundreds of angstroms, with possible implications for the uniformity of dopants incorporated in SiC devices during fabrication. The quantitative topographic data from the AFM allow the relevant defect information to be extracted, such as the size and distribution of step bunching and the Burgers vector of screw dislocations. These atomic force microscopy results have furthered the understanding of the dynamic epitaxial SiC growth process. A model describing the observed hillock step bunching has been proposed. This cooperation between researchers involved in crystal growth, electronic device fabrication, and surface structural characterization is likely to continue as atomic force microscopy is used to improve SiC films for high-temperature electronic devices for NASA's advanced turbine engines and space power devices, as well as for future applications in the automotive industry.

Source record↗
NASA NTRS1990

Programmable synaptic devices for electronic neural nets

The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

Moopenn, A.↗
NASA NTRS1981

Image readout device with electronically variable spatial resolution

An invention relating to the use of a standing acoustic wave charge storage device as an image readout device is described. A frequency f sub 1 was applied to the storage transfer device to create a traveling electric field in the device in one direction along a straight line. A second frequency f sub 2 was applied to the charge transfer device to create a traveling electric field opposite to the first traveling electric field. A standing wave was created. When an image was focused on the charge transfer device, light was stored in the wells of the standing wave. When the frequency f sub 2 is removed from the device, the standing wave tends to break up and the charges stored move to an electrode connected to an output terminal and to a utilization device where the received charges represent the image on the surface of the charge transfer device along a projection of said straight line.

Benz, H. A.↗
NASA NTRS1990

Solid-state reprogrammable analog resistive devices for electronic neural networks

The fabrication and performance of WO3-based, solid-state, three-terminal device configurations as programmable analog memory elements are reported. These transistorlike device structures exhibit good resistance progammability with a remarkable resolution of a few percent of the resistive strength over a four orders of magnitude dynamic range. The most critical component of these devices is an insulating layer between the active WO3 and the cation donor layer. The progamming characteristics and operation mechanisms of the device are described, and probable reaction mechanisms critical to the device stability are discussed.

Ramesham, R.↗
NASA NTRS2004

Portable Integrated Wireless Device Threat Assessment to Aircraft Radio Systems

An assessment was conducted on multiple wireless local area network (WLAN) devices using the three wireless standards for spurious radiated emissions to determine their threat to aircraft radio navigation systems. The measurement process, data and analysis are provided for devices tested using IEEE 802.11a, IEEE 802.11b, and Bluetooth as well as data from portable laptops/tablet PCs and PDAs (grouping known as PEDs). A comparison was made between wireless LAN devices and portable electronic devices. Spurious radiated emissions were investigated in the radio frequency bands for the following aircraft systems: Instrument Landing System Localizer and Glideslope, Very High Frequency (VHF) Communication, VHF Omnidirectional Range, Traffic Collision Avoidance System, Air Traffic Control Radar Beacon System, Microwave Landing System and Global Positioning System. Since several of the contiguous navigation systems were grouped under one encompassing measurement frequency band, there were five measurement frequency bands where spurious radiated emissions data were collected for the PEDs and WLAN devices. The report also provides a comparison between emissions data and regulatory emission limit.

Salud, Maria Theresa P.↗
NASA NTRS1999

Die Attachment for -120 C to +20 C Thermal Cycling of Microelectronics for Future Mars Rovers: An Overview

Active thermal control for electronics on Mars Rovers imposes a serious penalty in weight, volume, power consumption, and reliability. Thus, we propose that thermal control be eliminated for future Rovers. From a functional standpoint there is no reason that the electronics could not operate over the entire temperature range of the Martian environment, which can vary from a low of approximately equal -90 C to a high of approximately equal +20 C during the Martian night and day. The upper end of this range is well within that for conventional electronics. Although the lower end is considerably below that for which conventional--even high-reliability electronics is designed or tested, it is well established that electronic devices can operate to such low temperatures. The primary concern is reliability of the overall electronic system, especially in regard to the numerous daily temperature cycles that it would experience over the duration of a mission on Mars. Accordingly, key reliability issues have been identified for elimination of thermal control on future Mars Rovers. One of these is attachment of semiconductor die onto substrates and into packages. Die attachment is critical since it forms a mechanical, thermal and electrical interface between the electronic device and the substrate or package. This paper summarizes our initial investigation of existing information related to this issue, in order to form an opinion whether die attachment techniques exist, or could be developed with reasonable effort, to withstand the Mars thermal environment for a mission duration of approximately I year. Our conclusion, from a review of literature and personal contacts. is that die attachment can be made sufficiently reliable to satisfy the requirements of future Mars Rovers. Moreover, it appears that there are several possible techniques from which to choose and that the requirements could be met by judicious selection from existing methods using hard solders, soft solders, or organic adhesives. Thus from the standpoint of die attachment. it appears feasible to eliminate thermal control for Rover electronics. We recommend that this be further investigated and verified for the specific hardware and thermal conditions appropriate to Mars Rovers.

Kirschman, Randall K.↗
NASA NTRS1998

Simulation of Ultra-Small MOSFETs Using a 2-D Quantum-Corrected Drift-Diffusion Model

The continued down-scaling of electronic devices, in particular the commercially dominant MOSFET, will force a fundamental change in the process of new electronics technology development in the next five to ten years. The cost of developing new technology generations is soaring along with the price of new fabrication facilities, even as competitive pressure intensifies to bring this new technology to market faster than ever before. To reduce cost and time to market, device simulation must become a more fundamental, indeed dominant, part of the technology development cycle. In order to produce these benefits, simulation accuracy must improve markedly. At the same time, device physics will become more complex, with the rapid increase in various small-geometry and quantum effects. This work describes both an approach to device simulator development and a physical model which advance the effort to meet the tremendous electronic device simulation challenge described above. The device simulation approach is to specify the physical model at a high level to a general-purpose (but highly efficient) partial differential equation solver (in this case PROPHET, developed by Lucent Technologies), which then simulates the model in 1-D, 2-D, or 3-D for a specified device and test regime. This approach allows for the rapid investigation of a wide range of device models and effects, which is certainly essential for device simulation to catch up with, and then stay ahead of, electronic device technology of the present and future. The physical device model used in this work is the density-gradient (DG) quantum correction to the drift-diffusion model [Ancona, Phys. Rev. B 35(5), 7959 (1987)]. This model adds tunneling and quantum smoothing of carrier density profiles to the drift-diffusion model. We used the DG model in 1-D and 2-D (for the first time) to simulate both bipolar and unipolar devices. Simulations of heavily-doped, short-base diodes indicated that the DG quantum corrections do not have a large effect on the IN characteristics of electronic devices without heteroj unction s. On the other hand, ultra-small MOSFETs certainly exhibit important quantum effects that the DG model will include: quantum repulsion of the inversion and gate charges from the oxide interfaces, and quantum tunneling through thin gate oxides. We present initial results of 2-D DG simulations of ultra-small MOSFETs. Subtle but important issues involving the specification of the model, boundary conditions, and interface constraints for DG simulation of MOSFETs will also be illuminated.

Biegal, Bryan A.↗
NASA NTRS2008

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗
NASA NTRS2004

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Speer, Kevin M.↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

High temperature↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

electronic packaging↗
NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.

High Temperature, Packaging, Alumina, Thick Film↗
NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3 ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3 ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire - bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500oC are reviewed.

high temperature↗
NASA NTRS2001

Advanced Data Acquisition Systems with Self-Healing Circuitry

Kennedy Space Center's Spaceport Engineering & Technology Directorate has developed a data acquisition system that will help drive down the cost of ground launch operations. This system automates both the physical measurement set-up function as well as configuration management documentation. The key element of the system is a self-configuring, self-calibrating, signal-conditioning amplifier that automatically adapts to any sensor to which it is connected. This paper will describe the core technology behind this device and the automated data system in which it has been integrated. The paper will also describe the revolutionary enhancements that are planned for this innovative measurement technology. All measurement electronics devices contain circuitry that, if it fails or degrades, requires the unit to be replaced, adding to the cost of operations. Kennedy Space Center is now developing analog circuits that will be able to detect their own failure and dynamically reconfigure their circuitry to restore themselves to normal operation. This technology will have wide ranging application in all electronic devices used in space and ground systems.

Larson, William E.↗
NASA NTRS1986

GaAs Semi-Insulating Layer for a GaAs Device

Improved design for GaAs electronic device or integrated circuit designed to operate at cryogenic temperatures, customary SiO2 insulating layer replaced by semi-insulating layer of GaAs. Thermal expansions of device and covering layer therefore match closely, and thermal stresses caused by immersion in cryogenic chamber nearly eliminated.

Sherrill, G.↗
NASA NTRS1993

Upper-Bound SEU Rates In Anisotropic Fluxes

Upper bounds on rates of single-event upsets (SEU's) in digital integrated circuits and other electronic devices exposed to anisotropic fluxes of energetic ionizing particles computed by use of improved method. Derived from simplified, worst-case mathematical models of charge-collecting volumes and physical phenomena in electronic devices.

Edmonds, Larry D.↗
NASA NTRS2005

Electronic Transport through Self Assembled Thiol Molecules: Effect of Monolayer Order, Dynamics and Temperature

We present the charge transport and tunneling conductance of self assembled organic thiol molecules and discuss the influence of order and dynamics in the monolayer on the transport behavior and the effect of temperature. Conjugated thiol molecular wires and organometals such as terpyridine metal complexes provide a new platform for molecular electronic devices and we study their self assembly on Au(111) substrates by the scanning tunneling microscope. Determining the organization of the molecule and the ability to control the nature of its interface with the substrate is important for reliable performance of the molecular electronic devices. By concurrent scanning tunneling microscopy and spectroscopy studies on SAMs formed from oligo (phenelyne ethynelyne) monolayers with and without molecular order, we show that packing and order determine the response of a self assembled monolayer (SAM) to competing interactions. Molecular resolution STM imaging in vacuum shows that the OPES adopt an imcommensurate SAM structure on Au(111) with a rectangular unit cell. Tunneling spectroscopic measurements were performed on the SAM as a function of junction resistance. STS results show that the I-Vs are non linear and asymmetric due to the inherent asymmetry in the molecular structure, with larger currents at negative sample biases. The asymmetry increases with increasing junction resistance due to the asymmetry in the coupling to the leads. This is brought out clearly in the differential conductance, which also shows a gap at the Fermi level. We also studied the effect of order and dynamics in the monolayer on the charge transport and found that competing forces between the electric field, intermolecular interactions, tip-molecule physisorption and substrate-molecule chemisorption impact the transport measurements and its reliability and that the presence of molecular order is very important for reproducible transport measurements. Thus while developing new electronic platforms based on molecules, it is important to have a good control of the molecule-substrate interface, for the devices to perform reliably. While such a control would minimize fluctuations and dynamics in the ensemble, the real challenge is to develop device architectures that are tolerant to fluctuations, since they cannot be totally eliminated in these low dimensional soft systems. Results of temperature dependent STS measurements will also be discussed.

Dholakia, Geetha↗