Cadd - On-line synthesis of logic circuits
CADD on-line programming system for logic circuit synthesis
ON-LINE PROGRAMMING↗
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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Synthesizing Dynamic Programming Algorithms from Linear Temporal Logic Formulae
The problem of testing a linear temporal logic (LTL) formula on a finite execution trace of events, generated by an executing program, occurs naturally in runtime analysis of software. We present an algorithm which takes an LTL formula and generates an efficient dynamic programming algorithm. The generated algorithm tests whether the LTL formula is satisfied by a finite trace of events given as input. The generated algorithm runs in linear time, its constant depending on the size of the LTL formula. The memory needed is constant, also depending on the size of the formula.
Rosu, Grigore↗
Scheduling technique improvement study for advanced programs. Volume 3: Stage 1 advanced space transport program
Schedules and logic diagrams of manned reusable boost vehicle for advanced space transport program
Crain, D. P.↗
Hardware functional obfuscation with ferroelectric active interconnects
Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks.
42 ENGINEERING↗
A design procedure for radiation hardening certain NOR gate logic circuits.
Design procedure for production of radiation resistant NOR gate logic circuit
RADIATION RESISTANCE↗
AI-Guided Reasoning-Based Operator Support System for the Nuclear Power Plant Management
The Decision-making process in the Nuclear Power Plant (NPP) control room faces some challenges: operator incomplete knowledge, insufficient time for responding to the highly dynamic events, and a large number of indicators to monitor. Because of the complexity of the NPP system, it is hard to pre-plan all the failures/mitigative actions. An intelligent operator support system is vital to mitigate these shortcomings. In this paper, an AI declarative approach (Answer Set Programming (ASP)) is employed to represent our knowledge of the nuclear power plant in the form of logic rules. This represented knowledge is structured to form a reasoning-based operator support system. When an incident occurs, this ASP-based reasoning support system is demonstrated to be capable of fault identification (diagnosis), informing the operator of different scenarios and consequences, and generating the control options (decision making).
21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗
Standard Transistor Array (STAR). Volume 2, addendum 1: SIMLOG/TESTGN user's guide
A brief introduction to the SIMLOG/TESTGN system of programs is given. Detailed instructions on how to use the system are also included. SIMLOG is a logic simulation program. TESTGN is a test pattern generation program.
Carroll, B. D.↗
Scheduling technique improvement study for advanced programs. Volume 4: Ground support, test, training, investment, operations, advanced space transport program
Schedules and logic diagrams for ground support, testing, training, and management for advanced space transport program
Crain, D. P.↗
Design of a Ferroelectric Programmable Logic Gate Array
A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.
MacLeod, Todd C.↗
DALG: A program for test pattern generation in combinational logical circuits
A user's manual for a computer program DALG which generates test patterns for detecting faults in combinational logic circuits containing up to 200 logical gates is presented. The gates may be of logical types AND, OR, NAND, NOR, NOT, or Exclusive OR is presented. The faults may be any one gate or input struck at a fixed value (0 or 1). In addition to test pattern generation DALG will also determine whether or not the given test pattern will detect given faults in a circuit. Sample problems are given along with input data sheets and printed output to illustrate the capabilities of the program.
Source record↗
Use of NASTRAN as a teaching aid
Recent experiences with incorporating NASTRAN as a teaching tool in undergraduate courses was found pedagogically sound. Students with no previous computerized structures background are able to readily grasp the program's logic and begin solving realistic problems rapidly. The educational benefit is significantly enhanced by NASTRAN's plotting feature. However, the cost of operating the level 12 version makes the program difficult to justify.
Wilkinson, M. T.↗
Turbulence simulation mechanization for Space Shuttle Orbiter dynamics and control studies
The current version of the NASA turbulent simulation model in the form of a digital computer program, TBMOD, is described. The logic of the program is discussed and all inputs and outputs are defined. An alternate method of shear simulation suitable for incorporation into the model is presented. The simulation is based on a von Karman spectrum and the assumption of isotropy. The resulting spectral density functions for the shear model are included.
Tatom, F. B.↗
Research in mathematical theory of computation
Research progress in the following areas is reviewed: (1) new version of computer program LCF (logic for computable functions) including a facility to search for proofs automatically; (2) the description of the language PASCAL in terms of both LCF and in first order logic; (3) discussion of LISP semantics in LCF and attempt to prove the correctness of the London compilers in a formal way; (4) design of both special purpose and domain independent proving procedures specifically program correctness in mind; (5) design of languages for describing such proof procedures; and (6) the embedding of ideas in the first order checker.
Mccarthy, J.↗
Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets
An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.
Ng, Tak-kwong↗
Application of Artificial Intelligence (AI) programming techniques to tactical guidance for fighter aircraft
A research program investigating the use of Artificial Intelligence (AI) programming techniques to aid in the development of a Tactical Decision Generator (TDG) for Within-Visual-Range (WVR) air combat engagements is discussed. The application of AI methods for development and implementation of the TDG is presented. The history of the Adaptive Maneuvering Logic (AML) program is traced and current versions of the (AML) program is traced and current versions of the AML program are compared and contrasted with the TDG system. The Knowledge-Based Systems (KBS) used by the TDG to aid in the decision-making process are outlined and example rules are presented. The results of tests to evaluate the performance of the TDG against a version of AML and against human pilots in the Langley Differential Maneuvering Simulator (DMS) are presented. To date, these results have shown significant performance gains in one-versus-one air combat engagements.
Mcmanus, John W.↗
Application of Artificial Intelligence (AI) Programming Techniques to Tactical Guidance for Fighter Aircraft
A research program investigating the use of Artificial Intelligence (AI) techniques to aid in the development of a Tactical Decision Generator (TDG) for Within-Visual-Range (WVR) air combat engagements is discussed. The application of AI methods for development and implementation of the TDG is presented. The history of the Adaptive Maneuvering Logic (AML) program is traced and current versions of the AML program are compared and contrasted with the TDG system. The Knowledge-Based Systems (KBS) used by the TDG to aid in the decision-making process are outlined in detail and example rules are presented. The results of tests to evaluate the performance of the TDG versus a version of AML and versus human pilots in the Langley Differential Maneuvering Simulator (DMS) are presented. To date, these results have shown significant performance gains in one-versus-one air combat engagements, and the AI-based TDG software has proven to be much easier to modify than the updated FORTRAN AML programs.
McManus, John W.↗
A Rewriting-Based Approach to Trace Analysis
We present a rewriting-based algorithm for efficiently evaluating future time Linear Temporal Logic (LTL) formulae on finite execution traces online. While the standard models of LTL are infinite traces, finite traces appear naturally when testing and/or monitoring red applications that only run for limited time periods. The presented algorithm is implemented in the Maude executable specification language and essentially consists of a set of equations establishing an executable semantics of LTL using a simple formula transforming approach. The algorithm is further improved to build automata on-the-fly from formulae, using memoization. The result is a very efficient and small Maude program that can be used to monitor program executions. We furthermore present an alternative algorithm for synthesizing probably minimal observer finite state machines (or automata) from LTL formulae, which can be used to analyze execution traces without the need for a rewriting system, and can hence be used by observers written in conventional programming languages. The presented work is part of an ambitious runtime verification and monitoring project at NASA Ames, called PATHEXPLORER, and demonstrates that rewriting can be a tractable and attractive means for experimenting and implementing program monitoring logics.
Havelund, Klaus↗
Memory forensic analysis of a programmable logic controller in industrial control systems
In industrial control systems (ICS), programmable logic controllers (PLCs) are used to automate physical processes such as nuclear plants and power grid stations, and are often subject to cyber attacks. As in conventional IT domain, the memory analysis of the PLCs can help answer important forensic questions about the attack, such as the presence of malicious firmware, injection of modified control logic (the program running on the PLC), and manipulation of I/O devices (e.g., sensors and actuators). Unlike conventional IT domain, PLCs have heterogeneous hardware architecture, proprietary firmware and control software, making it challenging to employ a unified framework for their memory forensics. For merely extracting artifacts of forensic importance, reverse-engineering the firmware is a tedious task, and the effort needs to be repeated for every PLC model. As a community, a step-wise approach to tackle this challenge is to analyze the memory of specific PLCs, and subsequently find a generic framework applicable to all PLCs. Our work is a step forward in this direction. By following a methodology that focuses on the functional layer of PLCs instead of reverse engineering the firmware, we analyze the digital forensic artifacts available in a common PLC, Allen-Bradley ControlLogix 1756-L61. Before diving into the memory dump, we analyze the PLC control software to create a list of important artifacts that are sure to exist in the PLC memory dump. The approach employs a setup where PLC control software RSLogix-5000 is connected to the PLC, and the memory dump can be obtained as and when needed. We create test cases that sequentially highlight each category of artifacts, followed by an examination of the resultant impact on memory. After attaining the listed artifacts, we employ conventional string and known data searches to extract interesting information present in this PLC's memory. The memory analysis profile, presented as a Python library and shared with the community, can help a forensic investigator to readily extract forensic artifacts from the same model's controller. The adopted approach may help researchers in creating memory profile of other PLCs, and ultimately formulating a generic PLC memory analysis framework.
Rais, Muhammad Haris↗