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Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.
Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.
By including specific process modifications the effect of ion implantation on radiation hardness can be minimized and radiation hard ion implanted MOS circuits can be fabricated. The experimental procedure followed was to examine key processing steps (with respect to radiation hardness) on ion-implanted individual PMOS transistors. The individual transistors were evaluated by continuously monitoring the threshold voltage as the transistors were being irradiated. By comparing runs it was possible to deduce what is considered a radiation hard ion implanted process. Tests with a complex LSI PMOS IC processor chip containing over 2000 transistors and resistors were also conducted
Properties of second-gate electrode of MOS-FET AND application as voltage-controlled integrator
A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.
A gyrator circuit is described which is of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals feed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components, thereby stabilizing the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.
Cobalt 60 gamma radiation effect on MOS diodes fabricated on silicon substrates, noting surface state and oxide charge densities
This paper presents a mathematical model characterizing the behavior of a common-source amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the common-source amplifier is the most widely used amplifier in MOS technology, understanding and modeling the behavior of the FeFET-based common-source amplifier will help in the integration of FeFETs into many circuits.
This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.
The oxygen plasma oxidation of GaAs was studied in order to obtain extremely high frequency responses with MOS devices. In the multipole system a homogeneous oxygen plasma of high density can easily be obtained in a large volume. This system is thus convenient for the study of plasma oxidation of GaAs. The electrical properties of the MOS diodes obtained in this way are controlled by interface states, located mostly in the upper half of the band gap where densities in the 10 to the 13th power/(sq cm) (eV) range can be estimated. Despite these interface states the possibility of fabricating MOSFET transistors working mostly in the depletion mode for a higher frequency cut-off still exists.
Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.
Characterization results of a MOS controlled thyristor (MCTA60P60) are presented. This device is rated for 60A and for an anode to cathode voltage of -600 V. As discussed in the last report, the MCT failed during 500 V leakage tests at 200 C. In contrast to the BJT (bipolar junction transistor), MOSFET, and IGBT (insulated gate bipolar transistor) devices tested, the breakdown voltage of the MCT decreases significantly with increasing temperature.
The Composite Development Division of the Propulsion Laboratory at Marshall Space Flight Center (MSFC) is currently developing a class of electromechanical actuators (EMA's) for use in space transportation applications such as thrust vector control (TVC) and propellant control valves (PCV). These high power servomechanisms will require rugged, reliable, and compact power electronic modules capable of modulating several hundred amperes of current at up to 270 volts. MSFC has selected the brushless dc motor for implementation in EMA's. This report presents the results of an investigation into the applicability of two new technologies, MOS-controlled thyristors (MCT's) and pulse density modulation (PDM), to the control of brushless dc motors in EMA systems. MCT's are new power semiconductor devices, which combine the high voltage and current capabilities of conventional thyristors and the low gate drive requirements of metal oxide semiconductor field effect transistors (MOSFET's). The commanded signals in a PDM system are synthesized using a series of sinusoidal pulses instead of a series of square pulses as in a pulse width modulation (PWM) system. A resonant dc link inverter is employed to generate the sinusoidal pulses in the PDM system. This inverter permits zero-voltage switching of all semiconductors which reduces switching losses and switching stresses. The objectives of this project are to develop and validate an analytical model of the MCT device when used in high power motor control applications and to design, fabricate, and test a prototype electronic circuit employing both MCT and PDM technology for controlling a brushless dc motor.
Testing of the metal oxide semiconductor (MOS)-controlled thyristor (MCT) has uncovered a failure mechanism at elevated temperature. The failure appears to be due to breakdown of the gate oxide. Further testing is underway to verify the failure mode. Higher current level inverters were built to demonstrate 200 C operation of the N-MOSFET's and insulated-gate-bipolar transistors (IGBT's) and for life testing. One MOSFET failed early in testing. The origin of this failure is being studied. No IGBT's have failed. A prototype 28-to-42 V converter was built and is being tested at room temperature. The control loop is being finalized. Temperature stable, high value (10 micro-F) capacitors appear to be the limiting factor in the design at this time. In this application, the efficiency will be lower for the IGBT version due to the large V sub(cesat) (3.5-4 V) compared to the input voltage of 28 V. The MOSFET version should have higher efficiency; however, the MOSFET does not appear to be as robust at 200 C. Both versions are built for comparison.
An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.
Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.
The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.
It was found that ion beam texturing of silicon surfaces can be used to increase the effective surface area of MOS capacitors. There is, however, a problem with low dielectric breakdown. Preliminary work was begun on the fabrication of ion implanted resistors on textured surfaces and the potential improvement of wire bond strength by bonding to a textured surface. In the area of ion beam sputtering, the techniques for sputtering PVC were developed. A PVC target containing valinomycin was used to sputter an ion selective membrane on a field effect transistor to form a potassium ion sensor.