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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗
DOE OSTI2026

Bio-Inspired Energy-Efficient Nanofabricated Electrical Contacts

Nanoscale electrical contacts, especially those between materials of dissimilar electronic properties, often represent one of the main causes of drops in energy transfer efficiency. They are also among the sources of above-threshold noise, and their performance often decreases over the lifetime of the nanodevices. Scale-down limitations from mesoscopic to nanoscale devices, and likewise, of nanoscale to quantum-scale devices are also impeded by contacts’ quality. Making more reliable, energy-efficient electrical contacts is among the goals of the nanoelectronics research within the framework of energy-efficient electronic systems. This report focuses on the design, nanofabrication, and testing of novel shapes of electrical contacts. Lithography and nanofabrication were utilized to mimic the approximate shape of insect setae for mesoscale contacts design. The contacts are tested for elementary charge transport via I–V curves and for the broadband, 1/f noise. Tests show that contacts design leads to a measurable decrease in the energy necessary to operate a contact as a switch by at least 12–20%, depending on temperature, while broadband noise shows measurably lower power spectra, for bio-inspired contacts. The proposed method is open to modifications and improvements as required by various on-chip applications.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗
NASA NTRS1974

Yield analysis of large capacity magnetic bubble circuits with redundancy design

The fabrication yield of an on-chip modifiable redundant circuit design for a 100M bit serial shift register is evaluated. The yield model is a redundancy design in which there is a primary loop and a set of secondary loops which can be enabled/disabled without introducing blanks to the data stream. This function has a finite yield, the loop-modification yield factor, which must be greater than 0.9 to make the system more economical than the simple nonredundant design. It is further established that small loop capacities greatly degrade the yield because of the effect of the modification yield factor, while large loop capacities degrade the yield because of defects in the operating area. As the modification yield increases the optimum loop capacity decreases. An optimum value for the number of redundant loops exists for each loop capacity. Other factors that affect the yield are the garnet film and the processed circuit.

Bailey, R. F.↗
NASA NTRS1975

A 190 by 244 charge-coupled area image sensor with interline transfer organization

A 190 x 244 element charge coupled area image sensor has been designed, fabricated and tested. This sensor employs an interline transfer organization and buried n-channel technology. It features a novel on-chip charge integrator and a distributed floating gate amplifier for high and low light level applications. The X-Y element count has been chosen to establish the capability of producing an NTSC compatible video signal. The array size is also compatible with the Super 8 lens format. The first few sample devices have been successfully operated at full video bandwidth for both high and low light levels with the charge amplifier system.

Walsh, L. R.↗
NASA NTRS1975

Self-scanned Digicon - A digital image tube for astronomical spectroscopy

We have successfully fabricated, tested, and operated a digital image tube consisting of a magnetically focused image intensifier tube in which a self-scanned linear array of 1024 silicon photodiodes operating in the EBS mode serves as the photoelectron image detector, amplifier, and intermediate image storage device. Integral on-chip MOS shift registers driven by an external clock sequentially interrogate the photodiodes through MOS FET multiplex switch arrays. Each output frame is a sequence of 256 analog pulses on each of four video lines. Laboratory and observing tests show that the output signal is photoelectron shot noise limited over at least a range of 1-100,000 detected photoelectrons per picture element, indicating that single photon detection is achieved. High-resolution astronomical spectroscopy has been carried out in the coude spectrograph of the 2.7-m telescope at McDonald Observatory. Examples are shown.

Tull, R. G.↗
NASA NTRS1976

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 2: The optimization of material-device parameters for application in bubble domain memory elements for spacecraft data recorders

Bubble domain materials and devices are discussed. One of the materials development goals was a materials system suitable for operation of 16 micrometer period bubble domain devices at 150 kHz over the temperature range -10 C to +60 C. Several material compositions and hard bubble suppression techniques were characterized and the most promising candidates were evaluated in device structures. The technique of pulsed laser stroboscopic microscopy was used to characterize bubble dynamic properties and device performance at 150 kHz. Techniques for large area LPE film growth were developed as a separate task. Device studies included detector optimization, passive replicator design and test and on-chip bridge evaluation. As a technology demonstration an 8 chip memory cell was designed, tested and delivered. The memory elements used in the cell were 10 kilobit serial registers.

Besser, P. J.↗
NASA NTRS1976

Design automation for complex CMOS/SOS LSI hybrid substrates

A design automated approach used to develop thick-film hybrid packages is described. The hybrid packages produced combine thick-film and silicon on sapphire (SOS) laser surface interaction technologies to bring the on-chip performance level of SOS to the subsystem level. Packing densities are improved by a factor of eight over ceramic dual in-line packing; interchip wiring capacitance is low. Due to significant time savings, the design automated approach presented can be expected to yield a 3:1 reduction in cost over the use of manual methods for the initial design of a hybrid.

Ramondetta, P. W.↗
NASA NTRS1978

Integrated detector array preprocessing for infrared astronomical applications

On-board preprocessing of astronomical data from integrated infrared detector arrays and discrete detectors will allow increases in sensitivity and reductions in costs for observations from cryogenic space telescopes. A variety of preprocessing functions for this application, which could be implemented either through analog on-chip devices or through external microprocessors, is identified. Software simulations and laboratory evaluations are underway to determine the effectiveness of these preprocessing schemes.

Mccreight, C. R.↗
NASA NTRS1977

Bubble domain circuit organization

An on-chip bubble domain circuit organization. One or more storage registers are connected to a propagation path whereby data in the form of magnetic bubble domains (bubbles) may be transferred into and out of the storage registers. The propagation path includes a generator for producing the initial bubbles which are expanded into any desired number of new bubbles by a unique multiple output replicator. A unique input decoder is utilized to determine to which storage register the bubbles from the replicator will be directed along the propagation path. Those bubbles not selected may be annihilated. An output decoder utilizing essentially the same decoding scheme as the input decoder, selectively receives bubbles from the storage register. A transfer and replicate switch is utilized between the storage register and output decoder to selectively transfer bubbles to the output decoder. The output decoder may collapse all of the bubbles from certain storage registers so that only the information from the selected storage register reaches the detector. The detectors in turn produce the chip output signal. External control electronics are utilized to control the selective operation of the various devices utilized in the propagation path.

Chen, Thomas T.↗
DOE OSTI2025

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems

Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.

Limaye, Ankur M. (ORCID:0000000194062584)↗
DOE OSTI2025

Design and Performance of the SPT-SLIM Receiver Cryostat

The South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM) is a millimeter-wavelength line-intensity mapping experiment, which was deployed on the South Pole Telescope (SPT) during the 2024-2025 Austral summer season. This pathfinder experiment serves to demonstrate the on-sky operation of multi-pixel on-chip spectrometer technology. We report on the cryogenic performance of the SPT-SLIM receiver for the first year of commissioning observations. The SPT-SLIM receiver utilizes an Adiabatic Demagnetization Refrigerator (ADR) for cooling the focal plane of superconducting filterbank spectrometers to a temperature of 150 mK. We demonstrate stable thermal performance of the focal plane module during observations consistent with thermal modeling, enabling a cryogenic operating efficiency above 80%. We also report on the receiver control system design utilizing the Observatory Control System (OCS) platform for automated cryogenic operation on the SPT.

Young, M. R. [Fermilab; Chicago U., KICP]↗
DOE OSTI2025

An On-Sky Atmospheric Calibration of SPT-SLIM

We present the methodology and results of the on-sky responsivity calibration of the South Pole Telescope Shirokoff Line Intensity Mapper (SPT-SLIM). SPT-SLIM is a pathfinder line intensity mapping experiment utilizing the on-chip spectrometer technology, and was first deployed during the 2024-2025 Austral Summer season on the South Pole Telescope. During the two-week on-sky operation of SPT-SLIM, we performed periodic measurements of the detector response as a function of the telescope elevation angle. Combining these data with atmospheric opacity measurements from an on-site atmospheric tipping radiometer, simulated South Pole atmospheric spectra, and measured detector spectral responses, we construct estimates for the responsivity of SPT-SLIM detectors to sky loading. We then use this model to calibrate observations of the moon taken by SPT-SLIM, cross-checking the result against the known brightness temperature of the Moon as a function of its phase.

Dibert, K. R. [Chicago U., Astron. Astrophys. Ctr.↗
DOE OSTI2025

Obsidian

Obsidian A35 is a compact FPGA carrier board designed to interface with ADCs, DACs or other devices, either stand-alone or as an I/O expansion board. The connectivity includes 1 GigE, 4 SFP, 6 PMOD, FTDI USB and Arduino shield compatible header. The board features also a FPGA boot SPI Flash, on-chip DDR3 memory, VCXO and White Rabbit compatibility.

Moore, Victoria [Lawrence Berkeley National Labora↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
DOE OSTI2026

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗
DOE OSTI2026

A 3D-Printed Millimeter-Wave Inline Waveguide-to-Coplanar-Waveguide Transition to Enable Dense Spectrometer Arrays for Intensity Mapping Surveys

We present a 3D-printed millimeter-wave, octave-bandwidth, in-line waveguide-to-coplanar-waveguide transition designed to enable focal planes with dense arrays of on-chip spectrometers. These arrays will enable compelling surveys of the large-scale structure of the universe through millimeter-wave intensity mapping. The transition consists of a four-step ridge-waveguide transformer that couples light from a rectangular waveguide onto a coplanar waveguide via an electrical connection made with indium bump bonds. We develop a tolerance-aware optimization approach to identify high-performance transition geometries that are robust to manufacturing variations; the same formulation can be applied to other tolerance-sensitive design problems. We also describe the implementation of a custom apparatus and procedure for bump-bonding a silicon chip to a metallized 3D-printed component. We detail the fabrication of the coplanar waveguide chip and three-dimensional waveguide structure, simulations and metrology of a test device, and room temperature reflectance measurements of this device. The room temperature metrology and reflection measurements are consistent with a model that predicts a coupling efficiency of $\mathord{\sim} 95\%$ at cryogenic temperatures in the 85-170 GHz frequency range.

Stover, Austin [Chicago U.; Chicago U., KICP] (ORC↗