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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Development of a Thin-Film Solar Cell Interconnect for the Powersphere Concept

Dual junction amorphous silicon (a-Si) solar cells produced on polyimide substrate have been selected as the best candidate to produce a lightweight solar array for the PowerSphere program. The PowerSphere concept features a space-inflatable, geodetic solar array approximately 0.6 meters in diameter and capable of generating about 20W of electrical power. Trade studies of various wiring concepts and connection methods led to an interconnect design with a copper contact that wraps around the edge, to the back of the solar cell. Applying Plasma Vapor Deposited (PVD) copper film to both sides and the edge of the solar cell produces the wrap around contact. This procedure results in a contact pad on the back of the solar cell, which is then laser welded to a flex circuit material. The flex circuit is constructed of copper in a custom designed routing pattern, and then sandwiched in a Kapton insulation layer. The flex circuit then serves as the primary power distribution system between the solar cells and the spacecraft. Flex circuit material is the best candidate for the wiring harness because it allows for low force deployment of the solar cells by the inflatable hinges on the PowerSphere. An additional frame structure, fabricated and assembled by ILC Dover, will reinforce the wrap around contact-flex blanket connection, thus providing a mechanically robust solar cell interconnect for the PowerSphere multifunctional program. The PowerSphere team will use the wraparound contact design approach as the primary solution for solar cell integration and the flex blanket for power distribution.

Simburger, Edward J.↗
NASA NTRS2009

SiC Optically Modulated Field-Effect Transistor

An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification of the photon-detection signal. A family of operating curves characterizing the OFET can be generated in a series of measurements performed at different intensities of incident ultraviolet light.

Tabib-Azar, Massood↗
NASA NTRS2012

Apparatus and method of manufacture for an imager equipped with a cross-talk barrier

An imager apparatus and associated starting material are provided. In one embodiment, an imager is provided including a silicon layer of a first conductivity type acting as a junction anode. Such silicon layer is adapted to convert light to photoelectrons. Also included is a semiconductor well of a second conductivity type formed in the silicon layer for acting as a junction cathode. Still yet, a barrier is formed adjacent to the semiconductor well. In another embodiment, a starting material is provided including a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Also included is a second silicon layer disposed adjacent to the oxide layer opposite the first silicon layer. Such second silicon layer is further equipped with an associated passivation layer and/or barrier.

Pain, Bedabrata↗
NASA NTRS1996

Fast Risetime Reverse Bias Pulse Failures in SiC PN Junction Diodes

SiC-based high temperature power devices are being developed for aerospace systems which will require high reliability. One behavior crucial to power device reliability. To date, it has necessarily been assumed to date is that the breakdown behavior of SiC pn junctions will be similar to highly reliable silicon-based pn junctions. Challenging this assumption, we report the observation of anomalous unreliable reverse breakdown behavior in moderately doped (2-3 x 10(exp 17) cm(exp -3)) small-area 4H- and 6H-SiC pn junction diodes at temperatures ranging from 298 K (25 C) to 873 K (600 C). We propose a mechanism in which carrier emission from un-ionized dopants and deep level defects leads to this unstable behavior. The fundamental instability mechanism is applicable to all wide bandgap semiconductors whose dopants are significantly un-ionized at typical device operating temperatures.

Neudeck, Philip G.↗
NASA NTRS1980

A multiple p-n junction structure obtained from as-grown Czochralski silicon crystals by heat treatment - Application to solar cells

Multiple p-n junctions have been prepared in as-grown Czochralski p-type silicon through overcompensation near the oxygen periodic concentration maxima by oxygen thermal donors generated during heat treatment at 450 C. Application of the multiple p-n-junction configuration to photovoltaic energy conversion has been investigated. A new solar-cell structure based on multiple p-n-junctions was developed. Theoretical analysis showed that a significant increase in collection efficiency over the conventional solar cells can be achieved.

Chi, J. Y.↗
NASA NTRS2006

The USNA MIDN Microdosimeter Instrument

This paper describes the MIcroDosimetry iNstrument (MIDN) mission now under development at the United States Naval Academy. The instrument is manifested to fly on the MidSTAR-1 spacecraft, which is the second spacecraft to be developed and launched by the Academy s faculty and midshipmen. Launch is scheduled for 1 September 2006 on an ATLAS-5 launch vehicle. MIDN is a rugged, portable, low power, low mass, solid-state microdosimeter designed to measure in real time the energy distributions of energy deposited by radiation in microscopic volumes. The MIDN microdosimeter sensor is a reverse-biased silicon p-n junction array in a Silicon-On-Insulator (SOI) configuration. Microdosimetric frequency distributions as a function of lineal energies determine the radiation quality factors in support of radiation risk estimation to humans.

Pisacane, V. L.↗
NASA NTRS1984

Simultaneous junction formation

High-risk, high-payoff improvements to a baseline process sequence of simultaneous junction formation of silicon solar cells are discussed. The feasibility of simultaneously forming front and back junctions of solar cells using liquid dopants on dendritic web silicon was studied. Simultaneous diffusion was compared to sequential diffusion. A belt furnace for the diffusion process was tested.

Campbell, R. B.↗
NASA NTRS2018

Room Temperature Total-Ionizing Dose Testing of Glenn Research Center (GRC) 500 °C Durable 4H-SiC JFET IC Technology

The purpose of this testing was to obtain total ionizing dose (TID) information about custom-built research prototype silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) capable of prolonged operation in extremely high-temperature (500 degrees Centigrade) environments. The circuits included ring oscillators and operational amplifiers as well as individual n-channel JFETs. This technology is being considered for use in high temperature, high pressure applications such as Long-Lives Surface System Explorer (LLISSE). These devices were developed at NASA Glenn Research Center (GRC). Testing occurred from July 9th-July 13th, 2018.

Radiation↗
NASA NTRS2009

Structure for implementation of back-illuminated CMOS or CCD imagers

A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided, located opposite the passivation layer with respect to the epitaxial silicon layer, acting as a junction cathode. Prior to detection, light does not pass through a dielectric separating interconnection metal layers.

Pain, Bedabrata↗
NASA NTRS1976

A program continuation to develop processing procedures for advanced silicon solar cells

Shallow junctions, aluminum back surface fields and tantalum pentoxide (Ta205) antireflection coatings coupled with the development of a chromium-palladium-silver contact system, were used to produce a 2 x 4 cm wraparound contact silicon solar cell. One thousand cells were successfully fabricated using batch processing techniques. These cells were 0.020 mm thick, with the majority (800) made from nominal ten ohm-cm silicon and the remainder from nominal 30 ohm-cm material. Unfiltered, these cells delivered a minimum AMO efficiency at 25 C of 11.5 percent and successfully passed all the normal in-process and acceptance tests required for space flight cells.

Avery, J. E.↗
NASA NTRS1991

Tunnel junctions for InP-on-Si solar cells

Growing, by metalorganic chemical vapor deposition, a tunnel junction is described, which makes possible and ohmic back contact in an n-on-p InP solar cell on a silicon substrate. The junction between heavily doped layers of p-type InGaAs and n-type InP shows resistance low enough not to affect the performance of these cells. InP solar cells made on n-type Si substrates with this structure were measured with an efficiency of 9.9 percent. Controls using p-type GaAs substrates showed no significant difference in cell performance, indicating that the resistance associated with the tunnel junction is less than about 0.1 ohm/sq cm.

Keavney, C.↗
NASA NTRS1986

Flat-plate solar array project process development area: Process research of non-CZ silicon material

Several different techniques to simultaneously diffuse the front and back junctions in dendritic web silicon were investigated. A successful simultaneous diffusion reduces the cost of the solar cell by reducing the number of processing steps, the amount of capital equipment, and the labor cost. The three techniques studied were: (1) simultaneous diffusion at standard temperatures and times using a tube type diffusion furnace or a belt furnace; (2) diffusion using excimer laser drive-in; and (3) simultaneous diffusion at high temperature and short times using a pulse of high intensity light as the heat source. The use of an excimer laser and high temperature short time diffusion experiment were both more successful than the diffusion at standard temperature and times. The three techniques are described in detail and a cost analysis of the more successful techniques is provided.

Campbell, R. B.↗
NASA NTRS2008

SiC JFET Transistor Circuit Model for Extreme Temperature Range

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.↗
NASA NTRS1977

Application of the SEM to the measurement of solar cell parameters

Techniques are described which make use of the SEM to measure the minority carrier diffusion length and the metallurgical junction depth in silicon solar cells. The former technique permits the measurement of the true bulk diffusion length through the application of highly doped field layers to the back surfaces of the cells being investigated. It is shown that the secondary emission contrast observed in the SEM on a reverse-biased diode can depict the location of the metallurgical junction if the diode has been prepared with the proper beveled geometry. The SEM provides the required contrast and the option of high magnification, permitting the measurement of extremely shallow junction depths.

Weizer, V. G.↗
NASA NTRS1961

A Technique for Increasing the Sensitivity of a Solid-State Fission Probe

A small silicon p-n junction wafer, when coated with uranium 235, can be used as a compact fission probe for low power flux and power mapping. Because of the inverse relation between the magnitude of a neutron-induced fission pulse and the inherent capacitance of the detecting element (capacitance is proportional to area), the size, and hence the sensitivity, of the semiconductor detector has been limited. New developments in the field of semiconductor detectors have made it possible to fabricate large area detectors which are essentially free from the capacitance effect. However, preliminary results indicate that they are much more susceptible to radiation damage than the detectors described in this report and as such may not be suitable for flux mapping. increasing the sensitivity cannot be accomplished by simply fabricating a larger detector. It has been observed that by combining the silicon p-n junction wafers in a series configuration the capacitance effect can be bypassed, and a fission probe can be made with a resultant increase in sensitivity by a factor of ten while sustaining only a minor decrease in pulse height. Analysis further indicates that for n silicon wafers in series, if n(C(sub i)) + C(sub c)/C(sub b) less than 0.1 where C(sub i) and C(sub c) are the preamplifier input and cable capacitances, respectively, and C(sub b) is the junction capacitance of a single silicon wafer, there should be no substantial reduction in pulse height due to series circuitry.

Steinberg, Robert↗