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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Integrated High Payoff Rocket Propulsion Technology (IHPRPT) SiC Recession Model

SiC stability and recession rates were modeled in hydrogen/oxygen combustion environments for the Integrated High Payoff Rocket Propulsion Technology (IHPRPT) program. The IHPRPT program is a government and industry program to improve U.S. rocket propulsion systems. Within this program SiC-based ceramic matrix composites are being considered for transpiration cooled injector faceplates or rocket engine thrust chamber liners. Material testing under conditions representative of these environments was conducted at the NASA Glenn Research Center, Cell 22. For the study described herein, SiC degradation was modeled under these Cell 22 test conditions for comparison to actual test results: molar mixture ratio, MR (O2:H2) = 6, material temperatures to 1700 C, combustion gas pressures between 0.34 and 2.10 atm, and gas velocities between 8,000 and 12,000 fps. Recession was calculated assuming rates were controlled by volatility of thermally grown silica limited by gas boundary layer transport. Assumptions for use of this model were explored, including the presence of silica on the SiC surface, laminar gas boundary layer limited volatility, and accuracy of thermochemical data for volatile Si-O-H species. Recession rates were calculated as a function of temperature. It was found that at 1700 C, the highest temperature considered, the calculated recession rates were negligible, about 200 m/h, relative to the expected lifetime of the material. Results compared favorably to testing observations. Other mechanisms contributing to SiC recession are briefly described including consumption of underlying carbon and pitting. A simple expression for liquid flow on the material surface was developed from a one-dimensional treatment of the Navier-Stokes Equation. This relationship is useful to determine under which conditions glassy coatings or thermally grown silica would flow on the material surface, removing protective layers by shear forces. The velocity of liquid flow was found to depend on the gas velocity, the viscosity of gas and liquid, as well as the thickness of the gas boundary layer and the liquid layer. Calculated flow rates of a borosilicate glass coating compared well to flow rates observed for this coating tested on a SiC panel in Cell 22.

Opila, E. J.↗
NASA NTRS2010

Oxidation of TaSi2-Containing ZrB2-SiC Ultra-High Temperature Materials

Hot pressed coupons of composition ZrB2-20 v% SiC-5 v% TaSi2 and ZrB2-20 v% SiC-20 v% TaSi2 were oxidized in stagnant air at temperatures of 1627 and 1927C for one, five and ten 10-minute cycles. The oxidation reactions were characterized by weight change kinetics, x-ray diffraction, and SEM/EDS. Detailed WDS/microprobe quantitative analyses of the oxidation products were conducted for the ZrB2-20 v% SiC-20 v% TaSi2 sample oxidized for five 10-minute cycles at 1927C. Oxidation kinetics and product formation were compared to ZrB2-20 v% SiC with no TaSi2 additions. It was found that the 20 v% TaSi2 composition exhibited improved oxidation resistance relative to the material with no TaSi2 additions at 1627C. However, for exposures at 1927C less oxidation resistance and extensive liquid phase formation were observed compared to the material with no TaSi2 additions. Attempts to limit the liquid phase formation by reducing the TaSi2 content to 5 v% were unsuccessful. In addition, the enhanced oxidation resistance at 1627C due to 20 v% TaSi2 additions was not achieved at the 5 v% addition level. The observed oxidation product evolution is discussed in terms of thermodynamics and phase equilibria for the TaSi2-containing ZrB2-SiC material system. TaSi2-additions to ZrB2-SiC at any level are not recommended for ultra-high temperature (>1900C) applications due to excessive liquid phase formation.

Opila, Elizabeth J.↗
NASA NTRS2013

Packaging Technologies for 500C SiC Electronics and Sensors

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

Chen, Liang-Yu↗
NASA NTRS2016

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

Ikpe, Stanley A.↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗
NASA NTRSDate not supplied

DC Modeling of 4H-SiC JFET Gate Length Reduction at 500°C

The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460 °C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6μm (for recently fabricated Gen. 11 ICs) limits on mission relevant circuit capabilities [1]. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies to reduce the SiC JFET channel length while maintaining turn-off behavior (Fig. 1a) needed to realize 500 °C circuit operation. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1b) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. For the second fabrication strategy (Figure 1c), the high-dose phosphorous implants extended from below the contacts all the way up to the gate edges. Simulations guided gate length reductions without significant degradation in the turn-off performance. In total 12 SiC JFET variants implementing using the different fabrication strategies, gate lengths, and n-channel epilayer thickness were implemented in our simulation framework implemented in COMSOL. Since the COMSOL database does not have the material properties for 4H-SiC, these parameters were taken from the literature and implemented in COMSOL. The empirical models [2] for incomplete ionization, Auger recombination, low field mobility, and Shockley-Read-Hall recombination were implemented to account for material-specific device behavior.

4H-SiC JFET↗
NASA NTRS1984

Bubble formation in oxide scales on SiC

The oxidation of alpha-SiC single crystals and sintered alphaand beta-SiC polycrystals has been investigated at elevated temperatures. Bubble formation is commonly observed in oxide scales on polycrystalline SiC, but is rarely found on single-crystal scales; bubbles result from the preferential oxidation of C inclusions, which are abundant in SiC polycrystals. The absence of bubbles on single crystals, in fact, implies that diffusion of the gaseous species formed on oxidation, CO (or possibly SiO), controls the rate of oxidation of SiC.

Mieskowski, D. M.↗
NASA NTRS1988

Raman scattering studies of chemical-vapor-deposited cubic SiC films of (100)Si

Raman scattering studies for a series of CVD-grown cubic SiC single-crystal films with film thickness from 600 A to 17 microns are discussed. The results suggest that the crystalline orientations of the Si substrate and the 3C-SiC film are the same. It is found that the Si 522/cm phonon from a Si wafer is enhanced in intensity by a factor of 2-3 due to a CVD overlayer of cubic SiC, and that the 3C-SiC longitudinal optical phonon at the Gamma point from SiC/Si samples is enhanced by a factor of two or three following the removal of the Si substrate. The variation of the Raman spectrum with incident power is investigated, and a method for determining the Raman cross section for 3 C-SiC is proposed.

Feng, Z. C.↗
NASA NTRS1991

Thermochemical analysis of chemical processes relevant to the stability and processing of SiC-reinforced Si3N4 composite

Chemical processes relevant to the stability and processing of SiC-reinforced Si3N4 composites have been examined from thermochemical considerations. The thermodynamic stabilities of various interfaces, such as SiC-Si3N4, SiC-Si3N4-Si2ON2, and SiC-Si3N4-SiO2, have been examined as a function of temperature, and the temperatures above which these interfaces become unstable have been calculated. The degradation of SiC during the processing of the composite has been examined. The processing routes considered in this study include the reaction bonded silicon nitride (RBSN) process and the pressure-assisted sintering processes with suitable sintering additives.

Misra, Ajay K.↗
NASA NTRS1991

Correlated Si isotope anomalies and large C-13 enrichments in a family of exotic SiC grains

A hypothesis is presented to the effect that the distinctive morphological characteristics and comparatively simple Si isotope systematics identify the platy SiC crystals as a genetically related family, formed around a single isotopically heterogeneous presolar star on an association of related stars. The enrichments in C-13 and the Si isotope systematics of the platy SiC are broadly consistent with theoretical models of nucleosynthesis in low-mass, carbon stars on the ASG. The Si isotope array most plausibly reflects mixing between (Si-28)-rich material, inherited from a previous generation of stars, and material enriched in Si-29 and Si-30, produced in intershell regions by neutron capture during He-burning. The absence of a correlation between the Si and C isotopic compositions of the SiC suggests either episodic condensation of SiC, extending over several thermal pulses, in the atmosphere of a single star, or the derivation of the SiC from several stars characterized by different rates of C-13 production.

Stone, J.↗
NASA NTRS1992

SiC lightweight telescopes for advanced space applications. II - Structures technology

A critical technology area for lightweight SiC-based telescope systems is the structural integrity and thermal stability over spaceborne environmental launch and thermal operating conditions. Note, it is highly desirable to have an inherently athermal design of both SiC mirrors and structure. SSG has developed an 8 inch diameter SiC telescope system for brassboard level optical and thermal testing. The brassboard telescope has demonstrated less than 0.2 waves P-V in the visible wavefront change over +50 C to -200 C temperature range. SSG has also fabricated a SiC truss structural assembly and successfully qualified this hardware at environmental levels greater than 3 times higher than normal Delta, Titan, and ARIES launch loads. SSG is currently developing two SiC telescopes; an 20 cm diameter off-axis 3 mirror re-imaging and a 60 cm aperture on-axis 3 mirror re-imager. Both hardware developments will be tested to flight level environmental, optical, and thermal specifications.

Anapol, Michael I.↗
NASA NTRS1992

CVD of SiC and AlN using cyclic organometallic precursors

The use of cyclic organometallic molecules as single-source MOCVD precursors is illustrated by means of examples taken from our recent work on AlN and SiC deposition, with particular focus on SiC. Molecules containing (AlN)3 and (SiC)2 rings as the 'core structure' were employed as the source materials for these studies. The organoaluminum amide, (Me2AlNH2)3, was used as the AlN source and has been studied in a molecular beam sampling apparatus in order to determine the gas phase species present in a hot-wall CVD reactor environment. In the case of SiC CVD, a series of disilacyclobutanes (Si(XX')CH2)2 (with X and X' = H, CH3, and CH2SiH2CH3), were examined in a cold-wall, hot-stage CVD reactor in order to compare their relative reactivities and prospective utility as single-source CVD precursors. The parent compound, disilacyclobutane, (SiH2CH2)2, was found to exhibit the lowest deposition temperature (ca. 670 C) and to yield the highest purity SiC films. This precursor gave a highly textured, polycrystalline film on the Si(100) substrates.

Interrante, L. V.↗
NASA NTRS1993

Direct observation of porous SiC formed by anodization in HF

A process for forming porous SiC from single-crystal SiC wafers has been demonstrated. Porous SiC can be fabricated by anodizing n-type 6H-SiC in HF under UV illumination. TEM reveals pores of sizes 10-30 nm with interpore spacings ranging from roughly 5 to 150 nm. This is the first reported direct observation of porous SiC formation.

Shor, Joseph S.↗
NASA NTRS1998

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (less than 250 V) 4H-SiC p(+)n Junction diodes: DC Properties - Part 1

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = 1c with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4)/sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS1999

Study of Bulk and Elementary Screw Dislocation Assisted Reverse Breakdown in Low-Voltage (<250 V) 4H-SiC p+n Junction Diodes - Part 1: DC Properties

Given the high density (approx. 10(exp 4)/sq cm) of elementary screw dislocations (Burgers vector = lc with no hollow core) in commercial SiC wafers and epilayers, all appreciable current (greater than 1 A) SiC power devices will likely contain elementary screw dislocations for the foreseeable future. It is therefore important to ascertain the electrical impact of these defects, particularly in high-field vertical power device topologies where SiC is expected to enable large performance improvements in solid-state high-power systems. This paper compares the DC-measured reverse-breakdown characteristics of low-voltage (less than 250 V) small-area (less than 5 x 10(exp -4) sq cm) 4H-SiC p(+)n diodes with and without elementary screw dislocations. Compared to screw dislocation-free devices, diodes containing elementary screw dislocations exhibited higher pre-breakdown reverse leakage currents, softer reverse breakdown I-V knees, and highly localized microplasmic breakdown current filaments. The observed localized 4H-SiC breakdown parallels microplasmic breakdowns observed in silicon and other semiconductors, in which space-charge effects limit current conduction through the local microplasma as reverse bias is increased.

Neudeck, Philip G.↗
NASA NTRS1998

"Un-annealed and Annealed Pd Ultra-Thin Film on SiC Characterized by Scanning Probe Microscopy and X-ray Photoelectron Spectroscopy"

Pd/SiC has been used as a hydrogen and a hydrocarbon gas sensor operated at high temperature. UHV (Ultra High Vacuum)-Scanning Tunneling Microscopy (STM), Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS) techniques were applied to study the relationship between the morphology and chemical compositions for Pd ultra-thin films on SiC (less than 30 angstroms) at different annealing temperatures. Pd ultra-thin film on 6H-SiC was prepared by the RF sputtering method. The morphology from UHV-STM and AFM shows that the Pd thin film was well deposited on SiC substrate, and the Pd was partially aggregated to round shaped participates at an annealing temperature of 300 C. At 400 C, the amount of surface participates decreases, and some strap shape participates appear. From XPS, Pd2Si was formed on the surface after annealing at 300 C, and all Pd reacted with SiC to form Pd2Si after annealing at 400 C. The intensity of the XPS Pd peak decreases enormously at 400 C. The Pd film diffused into SiC, and the Schottky barrier height has almost no changes. The work shows the Pd sicilides/SiC have the same electronic properties with Pd/SiC, and explains why the Pd/SiC sensor still responds to hydrogen at high operating temperatures.

Lu, W. J.↗