Search NASA⌕ Search

SEARCH · Search NASA

Results for “VLSI circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Generating Weighted Test Patterns for VLSI Chips

Improved built-in self-testing circuitry for very-large-scale integrated (VLSI) digital circuits based on version of weighted-test-pattern-generation concept, in which ones and zeros in pseudorandom test patterns occur with probabilities weighted to enhance detection of certain kinds of faults. Requires fewer test patterns and less computation time and occupies less area on circuit chips. Easy to relate switching activity in outputs with fault-detection activity by use of probabilistic fault-detection techniques.

Siavoshi, Fardad↗
NASA NTRS1990

Concept For Generation Of Long Pseudorandom Sequences

Conceptual very-large-scale integrated (VLSI) digital circuit performs exponentiation in finite field. Algorithm that generates unusually long sequences of pseudorandom numbers executed by digital processor that includes such circuits. Concepts particularly advantageous for such applications as spread-spectrum communications, cryptography, and generation of ranging codes, synthetic noise, and test data, where usually desirable to make pseudorandom sequences as long as possible.

Wang, C. C.↗
NASA NTRS1992

Intelligent fuzzy controller for event-driven real time systems

Most of the known linguistic models are essentially static, that is, time is not a parameter in describing the behavior of the object's model. In this paper we show a model for synchronous finite state machines based on fuzzy logic. Such finite state machines can be used to build both event-driven, time-varying, rule-based systems and the control unit section of a fuzzy logic computer. The architecture of a pipelined intelligent fuzzy controller is presented, and the linguistic model is represented by an overall fuzzy relation stored in a single rule memory. A VLSI integrated circuit implementation of the fuzzy controller is suggested. At a clock rate of 30 MHz, the controller can perform 3 MFLIPS on multi-dimensional fuzzy data.

Grantner, Janos↗
NASA NTRS2003

Radiation tolerant back biased CMOS VLSI

A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

Maki, Gary K.↗
NASA NTRS1978

Fault tolerance using self-checking building-block computers

The paper attempts to define and characterize a set of VLSI (very large scale integration) building-block circuits which can be used to combine existing microprocessors and memories into a wide variety of fault-tolerant computing systems. Such VLSI circuits would transform fault-tolerant computing into an off-the-shelf technology and enable its routine use for new applications. The self-checking computer module (SCCM) is the basic component out of which fault-tolerant computer systems are constructed. Several fault-tolerant configurations of SCCM are discussed, including the standby redundant uniprocessor, the voted/hybrid uniprocessor, and the distributed computer network.

Rennels, D. A.↗
NASA NTRS1990

VLSI Architecture For Viterbi Decoder

"Pipeline" architecture developed for very-large-scale integrated (VLSI) Viterbi decoding circuits for binary convolutional codes of large constraint lengths. In scheme, single sequential processor computes path metrics in trellis diagram (diagram in which paths and nodes represent possible sequences of code states and in which metrics indicate relative likelihoods of sequences). Systolic-array method used to store path information as well as to choose path with best metric. VLSI Viterbi-decoder architecture is compromise between speed and complexity. Size of decoding circuit increases approximately linearly with constraint length of code, and additional circuit chips added with moderate numbers of interconnections.

Hsu, In-Shek↗
NASA NTRS1992

High-speed architecture for the decoding of trellis-coded modulation

Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

Osborne, William P.↗
NASA NTRS2003

Hybrid VLSI/QCA Architecture for Computing FFTs

A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

Fijany, Amir↗
NASA NTRS2003

Analog Binaural Circuits for Detecting and Locating Leaks

Very-large-scale integrated (VLSI) analog binaural signal-processing circuits have been proposed for use in detecting and locating leaks that emit noise in the ultrasonic frequency range. These circuits would be designed to function even in the presence of intense lower-frequency background noise that could include sounds associated with flow and pumping. Each of the proposed circuits would include the approximate electronic equivalent of a right and a left cochlea plus correlator circuits. A pair of transducers (microphones or accelerometers), corresponding to right and left ears, would provide the inputs to their respective cochleas from different locations (e.g., from different positions along a pipe). The correlation circuits plus some additional external circuits would determine the difference between the times of arrival of a common leak sound at the two transducers. Then the distance along the pipe from either transducer to the leak could be estimated from the time difference and the speed of sound along the pipe. If three or more pairs of transducers and cochlear/correlator circuits were available and could suitably be positioned, it should be possible to locate a leak in three dimensions by use of sound propagating through air.

Hartley, Frank T.↗
NASA NTRS1991

Competitive neural architecture for hardware solution to the assignment problem

The architecture for competitive assignment is described with attention given to the VLSI design and critical circuits fabricated in complementary metal-oxide semiconductor. The local application of association costs to processing units reduces the connectivity to the number of VLSI-compatible processing units. 'Hysteretic annealing' is discussed and when compared to mean-field annealing is found to enhance processing-unit gain and provide near-optimal solutions in about 150 microsec.

Eberhardt, S. P.↗
NASA NTRS1994

Low-Power CMOS Digital Autocorrelator Spectrometer

Prototype digital autocorrelator spectrometer circuit designed and built as assembly of few very-large-scale integrated (VLSI) complementary metal oxide/semiconductor (CMOS) circuit chips. Spectrometer contains 128 frequency channels and operates at clock rate of as much as 40 MHz. Total dc power needed is only 6 W. Digital autocorrelator spectrometer consists of four 32-channel autocorrelator chips that collectively produce 128-point spectrum of input signal as computed by use of Fourier transform.

Chandra, Kumar M.↗
NASA NTRS1981

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.

Rennels, D. A.↗
NASA NTRS1978

A study of standard building blocks for the design of fault-tolerant distributed computer systems

This paper presents the results of a study that has established a standard set of four semiconductor VLSI building-block circuits. These circuits can be assembled with off-the-shelf microprocessors and semiconductor memory modules into fault-tolerant distributed computer configurations. The resulting multi-computer architecture uses self-checking computer modules backed up by a limited number of spares. A redundant bus system is employed for communication between computer modules.

Rennels, D. A.↗
NASA NTRS1990

Custom CMOS Reed Solomon coder for the Hubble Space Telescope

A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

Whitaker, S.↗
NASA NTRS1983

Integrated control system concept for high-speed aircraft

The synthesis and evaluation of flight control system architectures for future aircraft are discussed in terms of design features and the requirements for fighter aircraft. Advanced fighter configurations may feature canards, flaperons, two-dimensional vectoring nozzles, a mixing compression inlet, and an advanced turbojet engine. Survey and evaluation technology will also progress to include distributed microprocessors, VLSI and VHSIC microcircuitry, optical circuits, analytic redundancy, etc. Bottom-p and top-down architectures have been investigated to fulfill the reliability, maintainability, cost, and performance goals. A centralized architecture has been devised with line-removable units to facilitate maintainability and reduce weight. Descriptions are provided of the performance parameters and applications of optical elements, photoelastic pressure sensors, rare earth sensors, computing elements, and information transfer system.

Carlin, C. M.↗
NASA NTRS1990

Next generation VLSI tools

This paper focuses on what features would be useful in VLSI Computer Aided Design Tools and Systems to be used in the next five to ten years. Examples of current design tasks will be used to emphasize the areas where new or expanded VLSI CAD tools are needed. To provide a basis for projecting the future of VLSI tools, a brief history of the evolution of VLSI design software and hardware platforms is presented. The role of design methodology is considered with respect to the anticipated scale of future VLSI design projects. Future requirements of design verification and manufacturing testing are projected based on the challenge of surviving in a competitive market. Examples of VLSI tools reflect the author's involvement on VLSI design teams developing integrated circuits for disk memory and other computer peripherals for the last eight years.

Gibson, J.↗
NASA NTRS1994

VLSI technology for smaller, cheaper, faster return link systems

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

Nanzetta, Kathy↗
NASA NTRS1993

Mixed voltage VLSI design

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

Panwar, Ramesh↗