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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS1986

Techniques for computing the discrete Fourier transform using the quadratic residue Fermat number systems

The complex integer multiplier and adder over the direct sum of two copies of finite field developed by Cozzens and Finkelstein (1985) is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplication over the rings of integers modulo Fermat numbers can be performed by means of two integer multiplications, whereas the complex integer multiplication requires three integer multiplications. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed to compute a systolic array of the DFT can be reduced substantially. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Truong, T. K.↗

NASA NTRS1988

Programmable pipelined image processor

A pipelined image processor selectively interconnects modules in a column of a two-dimensional array to modules of the next column of the array of modules 1,1 through M,N, where M is the number of modules in one dimension and N is the number of modules in the other direction. Each module includes two input selectors for A and B inputs, two convolvers, a binary function operator, a neighborhood comparison operator which produces an A output and an output selector which may select as a B output the output of any one of the components in the module, including the A output of the neighborhood comparison operator. Each module may be connected to as many as eight modules in the next column, preferably with the majority always in a different row that is up (or down) in the array for a generally spiral data path around the torus thus formed. The binary function operator is implemented as a look-up table addressed by the most significant 8 bits of each 12-bit argument. The table output includes a function value and the slopes for interpolation of the two arguments by multiplying the 4 least significant bits in multipliers and adding the products to the function value through adders.

Donald B Gennery↗

NASA NTRS1990

VLSI Reed-Solomon Encoder With Interleaver

Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

Hsu, In-Shek↗

NASA NTRS1990

A bit-serial VLSI array processing chip for image processing

An array processing chip integrating 128 bit-serial processing elements (PEs) on a single die is discussed. Each PE has a 16-function logic unit, a single-bit adder, a 32-b variable-length shift register, and 1 kb of local RAM. Logic in each PE provides the capability to mask PEs individually. A modified grid interconnection scheme allows each PE to communicate with each of its eight nearest neighbors. A 32-b bus is used to transfer data to and from the array in a single cycle. Instruction execution is pipelined, enabling all instructions to be executed in a single cycle. The 1-micron CMOS design contains over 1.1 x 10 to the 6th transistors on an 11.0 x 11.7-mm die.

Heaton, Robert↗

NASA NTRS1990

Serial multiplier arrays for parallel computation

Arrays of systolic serial-parallel multiplier elements are proposed as an alternative to conventional SIMD mesh serial adder arrays for applications that are multiplication intensive and require few stored operands. The design and operation of a number of multiplier and array configurations featuring locality of connection, modularity, and regularity of structure are discussed. A design methodology combining top-down and bottom-up techniques is described to facilitate development of custom high-performance CMOS multiplier element arrays as well as rapid synthesis of simulation models and semicustom prototype CMOS components. Finally, a differential version of NORA dynamic circuits requiring a single-phase uncomplemented clock signal introduced for this application.

Winters, Kel↗

NASA NTRS1993

Power optimization in logic isomers

Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.

Panwar, Ramesh↗

NASA NTRS1993

Correctness properties for iterated hardware structures

Iterated structures occur frequently in hardware. This paper describes properties required of mathematical relations that can be implemented iteratively and demonstrates the use of these properties on a generalized class of adders. This work provides a theoretical basis for the correct synthesis of iterated arithmetic structures.

Windley, Phillip J.↗

NASA NTRS1992

Evaluation of floating-point sum or difference of products in carry-save domain

An architecture to evaluate a 24-bit floating-point sum or difference of products using modified sequential carry-save multipliers with extensive pipelining is described. The basic building block of the architecture is a carry-save multiplier with built-in mantissa alignment for the summation during the multiplication cycles. A carry-save adder, capable of mantissa alignment, correctly positions products with the current carry-save sum. Carry propagation in individual multipliers is avoided and is only required once to produce the final result.

Wahab, A.↗

NASA NTRS1995

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

Kwatra, S. C.↗

NASA NTRS2004

Multi-Agent Methods for the Configuration of Random Nanocomputers

As computational devices continue to shrink, the cost of manufacturing such devices is expected to grow exponentially. One alternative to the costly, detailed design and assembly of conventional computers is to place the nano-electronic components randomly on a chip. The price for such a trivial assembly process is that the resulting chip would not be programmable by conventional means. In this work, we show that such random nanocomputers can be adaptively programmed using multi-agent methods. This is accomplished through the optimization of an associated high dimensional error function. By representing each of the independent variables as a reinforcement learning agent, we are able to achieve convergence must faster than with other methods, including simulated annealing. Standard combinational logic circuits such as adders and multipliers are implemented in a straightforward manner. In addition, we show that the intrinsic flexibility of these adaptive methods allows the random computers to be reconfigured easily, making them reusable. Recovery from faults is also demonstrated.

Lawson, John W.↗

NASA NTRS2001

An Approach for Self-Timed Synchronous CMOS Circuit Design

In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

Walker, Alvernon↗

NASA NTRS1989

VLSI processors for signal detection in SETI

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

NASA Program Exobiology↗

NASA NTRS2006

Evolutionary Based Techniques for Fault Tolerant Field Programmable Gate Arrays

The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.

Larchev, Gregory V.↗

NASA NTRS1993

Circuit and method for producing a flexible reference voltage

A flexible reference voltage circuit includes a circuit for producing a first digital signal representative of a range of reference voltage levels; a circuit for producing a second digital signal representative of a selected reference voltage level within the range of reference voltage levels; an adder for adding the first and second digital signals to produce a third digital signal; and a digital to analog converter for providing an output voltage in response to the third digital signal. The method of producing a flexible reference voltage performed by the circuit is also claimed. The invention can be used with a differential protection circuit to provide a series of trip level ranges, with a series of selectable trip levels in each range. This is accomplished in a high accuracy circuit which is relatively simple to construct, thereby minimizing size and complexity of the current sensor module, in differential protection applications, or the circuitry, if used in a power system controller. Standard digital logic components can be used to perform the necessary range/level decoding.

Thornton, Roger D.↗

NASA NTRS1997

High precision computing with charge domain devices and a pseudo-spectral method therefor

The present invention enhances the bit resolution of a CCD/CID MVM processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In another aspect of the invention, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neural network and the state function vector elements are treated as neurons. In a further aspect of the invention, moving target detection is performed by driving the soliton equation with a vector of detector outputs. The neural architecture consists of two synaptic arrays corresponding to the two differential terms of the soliton-equation and an adder connected to the output thereof and to the output of the detector array to drive the soliton equation.

Barhen, Jacob↗

NASA NTRS1984

Optical analog-to-digital converter

A method and apparatus for converting the intensity of an unknown optical signal (B) into an electrical signal in digital form utilizes two elongated optical attenuators (11, 13), one for the unknown optical signal from a source (10) and one for a known optical signal (A) from a variable source (12), a plurality of photodetectors (e.g., 17, 18) along each attenuator for detecting the intensity of the optical signals, and a plurality of comparators (e.g., 21) connected to the photodetectors in pairs to determine at what points being compared the attenuated known signal equals the attenuated unknown signal. The intensity of the unknown relative to the known is thus determined by the output of a particular comparator. That output is automatically encoded to a relative intensity value in digital form through a balancing feedback control (24) and encoder (23). The digital value may be converted to analog form in a D-to-A converter (27) and used to vary the source of the known signal so that the attenuated intensity of the known signal at a predetermined point (comparator 16) equals the attenuated intensity of the unknown signal at the predetermined point of comparison. If the known signal is then equal to the unknown, there is verification of the analog-to-digital conversion being complete. Otherwise the output of the comparator indicating equality at some other point along the attenuators will provide an output which is encoded and added, through an accumulator comprised of a register (25) and an adder (26), to a previous relative intensity value thereby to further vary the intensity of the known signal source. The steps are repeated until full conversion is verified.

Evanchuk, Vincent L.↗

NASA NTRS2007

Recent Advances in Photonic Devices for Optical Computing and the Role of Nonlinear Optics-Part II

The twentieth century has been the era of semiconductor materials and electronic technology while this millennium is expected to be the age of photonic materials and all-optical technology. Optical technology has led to countless optical devices that have become indispensable in our daily lives in storage area networks, parallel processing, optical switches, all-optical data networks, holographic storage devices, and biometric devices at airports. This chapters intends to bring some awareness to the state-of-the-art of optical technologies, which have potential for optical computing and demonstrate the role of nonlinear optics in many of these components. Our intent, in this Chapter, is to present an overview of the current status of optical computing, and a brief evaluation of the recent advances and performance of the following key components necessary to build an optical computing system: all-optical logic gates, adders, optical processors, optical storage, holographic storage, optical interconnects, spatial light modulators and optical materials.

Abdeldayem, Hossin↗

NASA NTRS2009

Universal programmable logic gate and routing method

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Fijany, Amir↗