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We report common base power amplifiers designed for 140-220 GHz frequency band in InP mesa double heterojunction bipolar transistor (DHBT) technology.
The project objective was to utilize two-phase heat transfer to enable compact and power-dense inverters. The high heat transfer capacity and near isothermal characteristics of two-phase cooling can enable higher power densities, reducing the size and cost of the power electronics system. This project focused on developing efficient, passive (no pump or compressor) two-phase cooling strategies that consist of an air-cooled condenser and evaporator. This report describes the modeling work conducted to design the evaporator and air-cooled condenser for a prototype inverter development work underway in the John Deere. Prototypes of the final evaporator and condenser designs were then fabricated via 3D printing for testing. Experiments on the evaporator confirmed that this component can meet the heat load and junction temperatures requirements for Si IGBT (insulated-gate bipolar transistor) inverter. Experiments with the air-cooled condenser were not possible due to leaks through the condenser walls.
Unity gain buffer amplifier with a Field Effect Transistor /FET/ differential input stage responds much faster than bipolar transistors when operated at low current levels. The circuit uses a dual FET in a unity gain buffer amplifier having extremely high input impedance, low bias current requirements, and wide bandwidth.
High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.
A wireless-controlled smart plug device and methods of use and operation, using a solid state switch to provide electrical power from an outlet to a load, and provide protection against overload, short circuit, ground, arc, or voltage surge faults. The switch includes a bidirectional semiconductor switch with two back-to-back connected transistors, such as silicon power MOSFETs, silicon insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) transistors, or gallium nitride (GaN) transistors, each configured to control the current flow from the electrical receptacle to the external electrical load.
proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors, which, by virtue of being identical to the input transistors, would reproduce the input differential potential at the output
The total ionizing dose response of ten bipolar transistor types has been measured using Co-60 gamma rays and 2.2 MeV electrons from exposure levels of 750, 1500, and 3000 Gy(Si). Gain measurements were made for a range of collector-emitter voltages and collector currents.
Uses VMOS field-effect power transistor. High-current drive circuit employs n-channel enhancement-mode VMOS field-effect power transistor to eliminate problem of oscillation at high power encountered in conventional circuits with bipolar transistors. Drive voltage required is typically 1 to 3 V for load current of 10 A.
Critical reappraisal of the bias dependence of the dc and small-signal ac current gain factors of planar bipolar transistors over a wide range of currents. This is based on a straightforward consideration of the three basic components of the dc base current arising due to emitter-to-base injected minority carrier transport, base-to-emitter carrier injection, and emitter-base surface depletion layer recombination effects. Experimental results on representative n-p-n and p-n-p silicon devices are given which support most of the analytical findings.
Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.
The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.
Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.
An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.
We report a single stage tunded amplifier that exhibits 7 dB small signal gain at 176 GHz. Common Base topology is chosen as it has the best maximum stable gain (MSG) in this frequency band when compared to common emitter and common collector topologies. The amplifiers are designed and fabricated in InP mesa double heterojunction bipolar transistor (DHBT) technology.
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as a function of charge collected from single-particle tracks which penetrate a bipolar static RAM. The results of this work provide a basis for the experimental verification of circuit-simulation SEU modeling in bipolar ICs.
A rigorous analytic evaluation of an emitter model that includes Auger recombination but excludes bandgap narrowing is presented. It is shown that such a model cannot explain the experimentally observed values of the open-circuit voltage in p-n-junction silicon solar cells. Thus physical mechanisms in addition to Auger recombination are responsible for the experimentally observed values of the open-circuit voltage in silicon solar cells and the common-emitter current gain in bipolar transistors.
Forward-bias tunneling is observed in heavily doped p-n junctions of bipolar transistors. A simple phenomenological model suitable to incorporation in device codes is developed. The model identifies as key parameters the space-charge-region (SCR) thickness at zero bias and the reduced doping level at its edges which can both be obtained from CV characteristics. This tunneling mechanism may limit the maximum gain achievable from scaled bipolar devices.
The tunability of polar and semiconducting properties of low-dimensional transition metal dichalcogenides (TMDs) have propelled them to the forefront of fundamental and applied physical research. These materials can vary their electrophysical properties from nonpolar to ferroelectric, and from direct-band semiconducting to metallic. In addition to classical controlling factors, such as field effect, composition, and doping, new degrees of freedom emerge in TMDs due to the curvature-induced electron redistribution and the associated changes in electronic properties. Here we theoretically explore the elastic and electric fields, flexoelectric polarization and free charge density for a TMD nanoflake placed on a rough substrate with a sinusoidal corrugation profile. Finite element modelling results for different flake thickness and corrugation depth yield insights into the flexoelectric nature of the out-of-plane electric polarization and establish the unambiguous correlation between the polarization and static conductivity modulation. The modulation is caused by the coupling between the deformation potential and inhomogeneous elastic strains, which evolve in the TMD nanoflake due to the adhesion between the flake surface and corrugated substrate. We reveal a pronounced maximum in the thickness dependences of the electron and hole conductivity of MoS 2 and MoTe 2 nanoflakes placed on a corrugated substrate, which opens the way for the optimization of their geometry towards significant improvement in their polar and electronic properties, necessary for advanced applications in nanoelectronics and memory devices. Specifically, the obtained results can be useful for the development of nanoscale straintronic devices based on the bended MoS 2 , MoTe 2 , and MoSTe nanoflakes, such as diodes and bipolar transistors with a bending-controllable sharpness of p-n junctions.