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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

Single chip fixed frequency bit synchronizer

A single chip, fixed frequency suboptimum bit synchronizer design which was implemented utilizing a programmable logic device is described. The bit synchronizer is modeled after a digital transition tracking loop for symbol estimation and employs a first-order incremental phase modulator for closed-loop symbol synchronization. The BER and tracking performance is modeled and compared to optimum designs. The bit synchronizer was developed for the Space Shuttle.

Butler, Madeline J.↗
NASA NTRS1991

The simulation of composite color imagery on 8-bit display devices

A transformation method has been developed that is very successful in simulating composite imagery and shows that, in general, 8-bit simulated composite images are almost indistinguishable from true composite imagery. This technique was designed to facilitate the display and interpretation of composite satellite imagery on display devices with only 256 displayable colors. The method is suitable for the combination of two 8-bit images into a single 8-bit composite image.

Thomason, Larry W.↗
NASA NTRS1992

Least reliable bits coding (LRBC) for high data rate satellite communications

LRBC, a bandwidth efficient multilevel/multistage block-coded modulation technique, is analyzed. LRBC uses simple multilevel component codes that provide increased error protection on increasingly unreliable modulated bits in order to maintain an overall high code rate that increases spectral efficiency. Soft-decision multistage decoding is used to make decisions on unprotected bits through corrections made on more protected bits. Analytical expressions and tight performance bounds are used to show that LRBC can achieve increased spectral efficiency and maintain equivalent or better power efficiency compared to that of BPSK. The relative simplicity of Galois field algebra vs the Viterbi algorithm and the availability of high-speed commercial VLSI for block codes indicates that LRBC using block codes is a desirable method for high data rate implementations.

Vanderaar, Mark↗
NASA NTRS1992

Applying an 8-bit multispectral color-composite image simulation technique to operational real-time AVHRR data

The Geophysics Directorate's 8-bit multispectral color-composite image display technique has been installed on the Satellite Data Processing System at the German Military Geophysical Office in Traben-Trarbach, Germany. The technique simulates 24-bit full-color composites on 8-bit color workstations, combining image data from the NOAA multispectral Advanced Very High Resolution Radiometer. The real-time application of this technique to operational satellite data is discussed.

Klaes, K. D.↗
NASA NTRS1992

Bit-parallel arithmetic in a massively-parallel associative processor

A simple but powerful new architecture based on a classical associative processor model is presented. Algorithms for performing the four basic arithmetic operations both for integer and floating point operands are described. For m-bit operands, the proposed architecture makes it possible to execute complex operations in O(m) cycles as opposed to O(m exp 2) for bit-serial machines. A word-parallel, bit-parallel, massively-parallel computing system can be constructed using this architecture with VLSI technology. The operation of this system is demonstrated for the fast Fourier transform and matrix multiplication.

Scherson, Isaac D.↗
NASA NTRS1990

A bit serial sequential circuit

Normally a sequential circuit with n state variables consists of n unique hardware realizations, one for each state variable. All variables are processed in parallel. This paper introduces a new sequential circuit architecture that allows the state variables to be realized in a serial manner using only one next state logic circuit. The action of processing the state variables in a serial manner has never been addressed before. This paper presents a general design procedure for circuit construction and initialization. Utilizing pass transistors to form the combinational next state forming logic in synchronous sequential machines, a bit serial state machine can be realized with a single NMOS pass transistor network connected to shift registers. The bit serial state machine occupies less area than other realizations which perform parallel operations. Moreover, the logical circuit of the bit serial state machine can be modified by simply changing the circuit input matrix to develop an adaptive state machine.

Hu, S.↗
NASA NTRS1984

NSC 800, 8-bit CMOS microprocessor

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.↗
NASA NTRS1998

Characterization of a 16-bit Digitizer System for Lidar Data Acquisition

A new 16-bit 6-MHz compact, lightweight waveform digitizer module has been tested using actual 300-nm lidar atmospheric returns. The noise level of this digitizer was tested and found to be substantially below the ozone number density to be measured. The digitizer is inexpensive and compact enough to be deployed in UAV aircraft and spacecraft environments. With 16-bit digitizers a resolution of 0.046 mV/step can be achieved, substantially improving resolution over 12-bit systems. This digitizer will find widespread use in future DIAL receiver systems.

Williamson, Cynthia K.↗
NASA NTRS2000

An Optical Bit-Counting Algorithm

This paper addresses the omnipresent problem of counting bits - an operation discussed since the very early stages of the establishing of computer science. The need for a quick bit-counting method acquires a special significance with the proliferation of search engines on the Internet. It arises in several other computer applications. This is especially true in information retrieval in which an array of binary vectors is used to represent a characteristic function (CF) of a set of qualified documents. The number of "I"s in the CF equals the cardinality of the set. The process of repeated evaluations of this cardinality is a pivotal point in choosing a rational strategy for deciding whether to constrain or broaden the search criteria to ensure selection of the desired items. Another need for bit-counting occurs when trying to determine the differences between given files, (images or text), in terms of the Hamming distance. An Exclusive OR operation applied to a pair of files results in a binary vector array of mismatches that must be counted.

Mack, Marilyn↗
NASA NTRS2002

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

flash memory program disturb wearout erase fail re↗
DOE OSTI2021

Bit error protection in cache memories

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Kalamatianos, John↗
DOE OSTI2019

Towards a bit threads derivation of holographic entanglement of purification

We apply the bit thread formulation of holographic entanglement entropy to reduced states describing only the geometry contained within an entanglement wedge. We argue that a certain optimized bit thread configuration, which we construct, gives a purification of the reduced state to a full holographic state obeying a precise set of conditional mutual information relations. When this purification exists, we establish, under certain assumptions, the conjectured E P = E W relation equating the entanglement of purification with the area of the minimal cross section partitioning the bulk entanglement wedge. Along the way, we comment on minimal purifications of holographic states, geometric purifications, and black hole geometries.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Demonstration of photonic micro-ring resonator based digital bit magnitude comparator

This paper details the novel design, simulation and analysis of the digital photonic single-bit magnitude comparator with the utilization of silicon micro-ring resonator as its core component. The micro-ring resonator uses electro-optic carrier injection modulation properties with its ring waveguide being structured in PIN diode. Five micro-ring resonators are used in the proposed design, with each corresponds to the specific logic mode operation. This work also presents the time varying simulation, where two predetermined 1-bit input stream is injected into the circuit at the data rate of 1 Gbps, where its output is observed via oscilloscope, where results are obtained at the sampling rate of 1.6 THz. The timing diagram for the entire simulation is also shown together with additional results obtained from the simulation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2017

Redundancy of einselected information in quantum Darwinism: The irrelevance of irrelevant environment bits [Separating the wheat from the chaff: Redundancy and relevant information in quantum Darwinism]

Here, the objective, classical world emerges from the underlying quantum substrate via the proliferation of redundant copies of selected information into the environment, which acts as a communication channel, transmitting that information to observers. These copies are independently accessible, allowing many observers to reach consensus about the state of a quantum system via its imprints in the environment. Quantum Darwinism recognizes that the redundancy of information is thus central to the emergence of objective reality in the quantum world. However, in addition to the “quantum system of interest,” there are many other systems “of no interest” in the Universe that can imprint information on the common environment. There is therefore a danger that the information of interest will be diluted with irrelevant bits, suppressing the redundancy responsible for objectivity. We show that mixing of the relevant (the “wheat”) and irrelevant (the “chaff”) bits of information makes little quantitative difference to the redundancy of the information of interest. Thus, we demonstrate that it does not matter whether one separates the wheat (relevant information) from the (irrelevant) chaff: The large redundancy of the relevant information survives dilution, providing evidence of the objective, effectively classical world.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
DOE OSTI2018

The Complexity of Bit Retrieval

Bit retrieval is the problem of reconstructing a periodic binary sequence from its periodic autocorrelation, with applications in cryptography and x-ray crystallography. After defining the problem, with and without noise, we describe and compare various algorithms for solving it. A geometrical constraint satisfaction algorithm, relaxed-reflect-reflect, is currently the best algorithm for noisy bit retrieval.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Analytical Bit-Error Model of NAND Flash Memories for Dosimetry Application

In this work, we provide an analytical model for the total ionizing dose (TID) effects on the bit error statistics of commercial flash memory chips. We have validated the model with experimental data collected by irradiating several commercial NAND flash memory chips from different technology nodes. We find that our analytical model can project bit errors at higher TID values (~ 20 krad(Si)) from measured data at lower TID values (<1 krad(Si)). Based on our model and the measured data, we have formulated basic design rules for using a commercial flash memory chip as a dosimeter. We discuss the impact of NAND chip-to-chip variability, noise margin and the intrinsic errors on the dosimeter design using detailed experimentation.

3-D NAND↗