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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
NASA NTRS1973

On the error probability of general tree and trellis codes with applications to sequential decoding

An upper bound on the average error probability for maximum-likelihood decoding of the ensemble of random binary tree codes is derived and shown to be independent of the length of the tree. An upper bound on the average error probability for maximum-likelihood decoding of the ensemble of random L-branch binary trellis codes of rate R = 1/n is derived which separates the effects of the tail length T and the memory length M of the code. It is shown that the bound is independent of the length L of the information sequence. This implication is investigated by computer simulations of sequential decoding utilizing the stack algorithm. These simulations confirm the implication and further suggest an empirical formula for the true undetected decoding error probability with sequential decoding.

Johannesson, R.↗
NASA NTRS1976

A new sequential decoder for the DSN telemetry subsystem

A sequential decoder was implemented in the DSS telemetry subsystem for the DSN MARK 3 data system implementation. This decoder performs the same decoding function as the data decoder assembly performs in the telemetry and command data handling subsystem. However, the new decoder is much faster, allowing potentially high data rates in the future.

Wilcher, J. H.↗
NASA NTRS1976

The fast decoding of Reed-Solomon codes using number theoretic transforms

It is shown that Reed-Solomon (RS) codes can be encoded and decoded by using a fast Fourier transform (FFT) algorithm over finite fields. The arithmetic utilized to perform these transforms requires only integer additions, circular shifts and a minimum number of integer multiplications. The computing time of this transform encoder-decoder for RS codes is less than the time of the standard method for RS codes. More generally, the field GF(q) is also considered, where q is a prime of the form K x 2 to the nth power + 1 and K and n are integers. GF(q) can be used to decode very long RS codes by an efficient FFT algorithm with an improvement in the number of symbols. It is shown that a radix-8 FFT algorithm over GF(q squared) can be utilized to encode and decode very long RS codes with a large number of symbols. For eight symbols in GF(q squared), this transform over GF(q squared) can be made simpler than any other known number theoretic transform with a similar capability. Of special interest is the decoding of a 16-tuple RS code with four errors.

Reed, I. S.↗
NASA NTRS1979

On the distribution of computation for sequential decoding using the stack algorithm

A method is developed for estimating the computational distribution for the stack algorithm for sequential decoding, that is, the probability that the computation required to decode the first branch of the tree is greater than or equal to N, for small N. The analysis relies heavily on the theory of multitype branching processes. A step in the analysis is the determination of the distribution of the minimum of the cumulative metrics along the transmitted path in the code tree. This is used to obtain the distribution of the number of computations made by the decoder in order to decode the first branch in the tree, and this random variable serves as an approximation of the average number of computations per decoded branch. At information rates below the cutoff rate, the calculated computational performance is virtually identical to that obtained by time-consuming simulations.

Johannesson, R.↗
NASA NTRS1983

Symbol synchronization for the TDRSS decoder

Each 8 bits out of the Viterbi decoder correspond to one symbol of the R/S code. Synchronization must be maintained here so that each 8-bit symbol delivered to the R/S decoder corresponds to an 8-bit symbol from the R/S encoder. Lack of synchronization, would cause an error in almost every R/S symbol since even a - 1-bit sync slip shifts every bit in each 8-bit symbol by one position, therby confusing the mapping betweeen 8-bit sequences and symbols. The error correcting capability of the R/S code would be exceeded. Possible ways to correcting this condition include: (1) designing the R/S decoder to recognize the overload and shifting the output sequence of the inner decoder to establish a different sync state; (2) using the characteristics of the inner decoder to establish symbol synchronization for the outer code, with or without a deinterleaver and an interleaver; and (3) modifying the encoder to alternate periodically between two sets of generators.

Costello, D. J., Jr.↗
NASA NTRS1983

Decoders for MST radars

Decoding techniques and equipment used by MST radars are described and some recommendations for new systems are presented. Decoding can be done either by software in special-purpose (array processors, etc.) or general-purpose computers or in specially designed digital decoders. Both software and hardware decoders are discussed and the special case of decoding for bistatic radars is examined.

Woodman, R. F.↗
NASA NTRS1986

Modular VLSI Reed-Solomon Decoder

Proposed Reed-Solomon (RS) decoder assembled from very-large-scale integrated-circuit (VLSI) building blocks. Decoder exploits recursive forms in RS decoding algorithms. RS codes capable of correcting random or burst errors in telemetry and other data-communication signals. Because of small size and low power consumption, advantageous to employ several such decoders in parallel-processing scheme to increase decoding speed.

Liu, K. Y.↗
NASA NTRS1985

Error-trellis syndrome decoding techniques for convolutional codes

An error-trellis syndrome decoding technique for convolutional codes is developed. This algorithm is then applied to the entire class of systematic convolutional codes and to the high-rate, Wyner-Ash convolutional codes. A special example of the one-error-correcting Wyner-Ash code, a rate 3/4 code, is treated. The error-trellis syndrome decoding method applied to this example shows in detail how much more efficient syndrome decordig is than Viterbi decoding if applied to the same problem. For standard Viterbi decoding, 64 states are required, whereas in the example only 7 states are needed. Also, within the 7 states required for decoding, many fewer transitions are needed between the states.

Reed, I. S.↗
NASA NTRS1985

Erasure information for a Reed-Solomon decoder

Many Reed-Solomon decoders, including the one decoding the outer code for Voyager data from Uranus, assume that all symbols have the same chance of being correct or incorrect. Insome cases, like in a burst of incorrect symbols, this is not the case, and a Reed-Solomon decoder could make use of this. The use of information about bit quality sent to the Reed-Solomon from an (inner) Viterbi decoder is examined, as well as information about the error status of adjacent symbols in decoding interleaved Reed-Solomon encoded symbols. It is discovered that, in a region of interest, only about 0.04 dB can gained.

Pitt, G. H., III↗
NASA NTRS1989

Quantization effects in Viterbi decoding rate 1/n convolutional codes

A Viterbi decoder's performance loss due to quantizing data from the additive white Gaussian noise (AWGN) channel is studied. An optimal quantization scheme and branch metric calculation method are presented. The uniformly quantized channel capacity C(sub u)(q) is used to determine the smallest number of quantization bits q that does not cause a significant loss. The quantizer stepsize which maximizes C(sub u)(q) almost minimizes the decoder bit error rate (BER). However, a slightly larger stepsize is better, like the value that minimizes the Bhattacharyya bound. The range and renormalization of state metrics is analyzed, in particular for K = 15 decoders such as the Big Viterbi Decoder (BVD) for the Galileo mission. These results are required to design reduced hardware complexity Viterbi decoders with a negligible quantization loss.

Onyszchuk, I. M.↗
NASA NTRS1991

Multi-stage decoding of multi-level modulation codes

Various types of multi-stage decoding for multi-level modulation codes are investigated. It is shown that if the component codes of a multi-level modulation code and types of decoding at various stages are chosen properly, high spectral efficiency and large coding gain can be achieved with reduced decoding complexity. Particularly, it is shown that the difference in performance between the suboptimum multi-stage soft-decision maximum likelihood decoding of a modulation code and the single-stage optimum soft-decision decoding of the code is very small, only a fraction of dB loss in signal to noise ratio at a bit error rate (BER) of 10(exp -6).

Lin, Shu↗
NASA NTRS1992

High-speed architecture for the decoding of trellis-coded modulation

Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

Osborne, William P.↗
NASA NTRS1991

High resolution decoding of Multi-Anode Microchannel Array detectors

The Multi-Anode Microchannel Array (MAMA) is a photon counting detector which utilizes a photocathode for photon to electron conversion, a microchannel plate (MCP) for signal amplification and a proximity focused anode array for position sensitivity. The detector electronics decode the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. A new algorithm incorporated into a CMOS Application Specific Integrated Circuit (ASIC) decoder which improves the pixel spatial resolution is described. The new algorithm does not degrade the detector throughput and does not require any modifications to the detector tube. The standard MAMA detector has a pixel size of 25 x 25 square microns, but with the new decoder circuit the pixel size is reduced to 12.5 x 12.5 square microns. We have built the first set of decode electronics utilizing the new ASIC chips and report here on the first imaging tests of this system.

Kasle, David B.↗
NASA NTRS1997

Complementary Reliability-Based Decodings of Binary Linear Block Codes

This correspondence presents a hybrid reliability-based decoding algorithm which combines the reprocessing method based on the most reliable basis and a generalized Chase-type algebraic decoder based on the least reliable positions. It is shown that reprocessing with a simple additional algebraic decoding effort achieves significant coding gain. For long codes, the order of reprocessing required to achieve asymptotic optimum error performance is reduced by approximately 1/3. This significantly reduces the computational complexity, especially for long codes. Also, a more efficient criterion for stopping the decoding process is derived based on the knowledge of the algebraic decoding solution.

Fossorier, Marc P. C.↗
NASA NTRS2004

A Scalable Architecture of a Structured LDPC Decoder

We present a scalable decoding architecture for a certain class of structured LDPC codes. The codes are designed using a small (n,r) protograph that is replicated Z times to produce a decoding graph for a (Z x n, Z x r) code. Using this architecture, we have implemented a decoder for a (4096,2048) LDPC code on a Xilinx Virtex-II 2000 FPGA, and achieved decoding speeds of 31 Mbps with 10 fixed iterations. The implemented message-passing algorithm uses an optimized 3-bit non-uniform quantizer that operates with 0.2dB implementation loss relative to a floating point decoder.

optical communications↗
NASA NTRS1989

Method and apparatus for implementing a traceback maximum-likelihood decoder in a hypercube network

A method and a structure to implement maximum-likelihood decoding of convolutional codes on a network of microprocessors interconnected as an n-dimensional cube (hypercube). By proper reordering of states in the decoder, only communication between adjacent processors is required. Communication time is limited to that required for communication only of the accumulated metrics and not the survivor parameters of a Viterbi decoding algorithm. The survivor parameters are stored at a local processor's memory and a trace-back method is employed to ascertain the decoding result. Faster and more efficient operation is enabled, and decoding of large constraint length codes is feasible using standard VLSI technology.

Pollara-Bozzola, Fabrizio↗
NASA NTRS2009

Bounded-Angle Iterative Decoding of LDPC Codes

Bounded-angle iterative decoding is a modified version of conventional iterative decoding, conceived as a means of reducing undetected-error rates for short low-density parity-check (LDPC) codes. For a given code, bounded-angle iterative decoding can be implemented by means of a simple modification of the decoder algorithm, without redesigning the code. Bounded-angle iterative decoding is based on a representation of received words and code words as vectors in an n-dimensional Euclidean space (where n is an integer).

Dolinar, Samuel↗
NASA NTRS2003

VLSI design of turbo decoder for integrated communication system on a chip applications

A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as satellite communications, wireless LAN, digital TV, cable modem, Digital Video Broadcast (DVB), and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides Forward Error Correction of up to 15 Mbits/sec on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watts.

turbo decoder↗