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Commutation by field-effect transistor allows more efficient operation. High voltage field-effect transistor (FET) controls silicon controlled rectifiers (SCR's). Circuit requires only one capacitor and one inductor in commutation circuit: simpler, more efficient, and more economical than conventional inverters. Adaptable to dc-to-dc converters.
A 128-element InSb linear detector array read out with a field effect transistor (FET) multiplexing scheme has been developed at the Jet Propulsion Laboratory. State-of-the-art NEP, uniform response, on-detector charge integration, and very low focal plane heat load compared to that of discrete detector arrays allows this type of array to open new possibilities for spaceborne near-infrared imaging spectrometers. Large number of cooled detector elements are feasible with the new technology, making it practical to design sensitive spectrometers even for spinning spacecraft where simultaneous wavelength coverage is necessary to avoid confusion of spatial with spectral variations.
The maturity of the molecular beam epitaxy (MBE) technique for preparing device quality GaAs material for microwave applications is demonstrated by the excellent performance characteristics of K-band GaAs power field-effect transistors (FETs) fabricated on the MBE wafers. An output power of 710 mW with 4.5-dB gain and 17.7 percent power-added efficiency was achieved at 21 GHz with a 1.26-mm gate width pi-gate device. A similar device with a 0.56-mm gate width produced an output power of 320 mW with 5.0-dB gain and 26.6 percent power-added efficiency at 21 GHz. These are the best results yet reported to date for GaAs power FETs operated in the K-band frequency range.
A transformer induced oscillation in series resonant (SR) converters is studied. It may occur in the discontinuous current mode. The source of the oscillation is an unexpected resonant circuit formed by normal resonance components in series with the magnetizing inductance of the output transformers. The methods for achieving cyclic stability are: to use a half bridge SR converter where q0.5. Q should be as close to 1.0 as possible. If 0.5q1.0, the instability will be avoided if psi2/3q-1/3. The second objective was to investigate a power field effect transistor (FET) version of the SR converter capable of operating at frequencies above 100 KHz, to study component stress and losses at various frequencies.
The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of 'slow' states can interfere with the interface-state measurements.
New low-noise cryogenic input transmission lines have been developed for the Deep Space Network (DSN) at 1.668 GHz for cryogenically cooled Field Effect Transistors (FET) and High Electron Mobility Transistor (HEMT) amplifiers. These amplifiers exhibit very low noise temperatures of 5 K to 15 K, making the requirements for a low-noise input transmission line critical. Noise contribution to the total amplifier system from the low-noise line is less than 0.5 K for both the 1.668-GHz and 2.25-GHz FET systems. The 1.668-GHz input line was installed in six FET systems which were implemented in the DSN for the Venus Balloon Experiment. The 2.25-GHz input line has been implemented in three FET systems for the DSN 34-m HEF antennas, and the design is currently being considered for use at higher frequencies.
The Very Large Array (VLA) is being equipped to receive telemetry from Voyager 2 during the Neptune encounter in 1989. Cryogenically cooled amplifiers are being installed on each of the 27 antennas. These amplifiers are currently a mix of field effect transistors (FETs) and high electron mobility transistors (HEMTs) and exhibit zenith system temperatures that range from 30 to 52 K. The system temperatures and aperture efficiencies determined during the past year are summarized. The nominal values of the noise diode calibration are compared with derived values made under the assumption of a uniform atmosphere over the array. Gain values are determined from observations of unresolved radio sources whose flux densities are well known. The tests suggest that the completed VLA will have a ratio of gain to system temperature that is approximately 4.4 dB above that of a single 64 m antenna of the Deep Space Network.
The use of liquid and gas phase sulfur pretreatment of the surface of InP as a way to form a near-ideal passivated surface prior to chemical vapor deposition of SiO2 was investigated. Results of high-frequency and quasi-static capacitance-voltage measurements, as well as enhancement mode insulated gate field-effect transistor (FET) transductance and drain current stability studies, all support the efficacy of this approach for metal-insulator-semiconductor application of this semiconductor. In particular, surface state values in the range of 10 to the 10th to a few 10 to the 11th/sq cm per eV and enhancement mode FET drain current drifts of less than 5 percent over a 12 h test period were measured.
Gallium arsenide integrated-circuit chip switches any of three microwave input signals to any of three output ports. Measuring 4.9 mm on side, chip contains nine field-effect transistor (FET) crosspoint switches. Housed in custom-designed package with standard connectors for easy integration into system. FET's on chip operated as passive switches and consume no static power and insignificant amounts of switching power. Chip module cascades with similar modules into large arrays handling as many as 100 inputs and 100 outputs. Applications include switching and routing vast amounts of data between computers at extremely high speed. On communications satellite, chip switches microwave signals to and from Earth stations and other satellites.
Advantages include reduced power and high speed. Experimental gallium arsenide field-effect-transistor (FET) domino circuit replicated in large numbers for use in dynamic-logic systems. Name of circuit denotes mode of operation, which logic signals propagate from each stage to next when successive stages operated at slightly staggered clock cycles, in manner reminiscent of dominoes falling in a row. Building block of domino circuit includes input, inverter, and level-shifting substages. Combinational logic executed in input substage. During low half of clock cycle, result of logic operation transmitted to following stage.
Neither external bias nor energy-storage components required. Three-terminal semiconductor switching circuit features high switching speed, extremely high turnoff safe operating area (area in current-vs-voltage plane), moderately low forward ("on"-state) voltage drop, and efficient utilization of silicon in design of components. Includes gate-turn-off thyristor (GTO) and low-voltage (low-on-resistance) field-effect transistor (FET-1) connected in series to form cascode pair. Made of commercially available, discrete components, as hybrid circuit package or as monolithic integrated circuit.
Researchers studied the InAs/AlSb system recently, obtaining 12nm wide quantum wells with room temperature mobilities up to 28,000 cm(exp 2)/V center dot S and low-temperature mobilities up to 325,000 cm(exp 2)/V center dot S, both at high electron sheet concentrations in the 10(exp 12)/cm(exp 2) range (corresponding to volume concentrations in the 10(exp 18)/cm(exp 2) range). These wells were not intentionally doped; the combination of high carrier concentrations and high mobilities suggest that the electrons are due to not-intentional modulation doping by an unknown donor in the AlSb barriers, presumably a stoichiometric defect, like an antisite donor. Inasmuch as not intentionally doped bulk AlSb is semi-insulating, the donor must be a deep one, being ionized only by draining into the even deeper InAs quantum well. The excellent transport properties are confirmed by other observations, like excellent quantum Hall effect data, and the successful use of the quantum wells as superconductive weak links between Nb electrodes, with unprecendentedly high critical current densities. The system is promising for future field effect transistors (FETs), but many processing problems must first be solved. Although the researchers have achieved FETs, the results so far have not been competitive with GaAs FETs.
Noise-optimal control of high-electron mobility transistor low noise amplifier (HEMT LNA) bias voltage and current values was achieved at room temperature. The performance metric maximized was the amplifier gain divided by the amplifier input noise temperature, G/T(sub e). Additionally, the feasibility of automating the initial determination of bias settings was demonstrated in the laboratory. Simulation models of an HEMT were developed from available measurement data, installed on a Sun SPARC 1 workstation, and used in investigating several optimization algorithms. Simple tracking-type algorithms, which follow changes in optimum settings if started at or near the global optimum point, produced the best performance. Implementation of the optimization algorithms was performed using a three-stage Field Effect Transistor (FET) LNA and an existing test apparatus. Software was written to control the bias settings of the first stage of the LNA and to perform noise and gain measurements by using the test apparatus. The optimization control was then integrated with existing test software to create a master test and optimization program for test apparatus use.
The quasi-optical generations of images of objects with their internal structure in millimeter (MM) and submillimeter (SMM) bands is one of prime problems of modern radioelectronics. The main advantage of passive MM imaging systems in comparison with visible and infrared (IR) systems is small attenuation of signals in fog, cloud, smoke, dust and other obscurants. However, at a panoramic scanning of space the observation time lengthens and thereby the information processing rate becomes restricted so that single-channel system cannot image in real time. Therefore we must use many radiometers in parallel to reduce the observation time. Such system must contain receiving sensors as pixels in multibeam antenna. The use of Josephson Junctions (JJ) for this purpose together with the cryoelectronic devices like GaAs FET (field effect transistors) or SQUIDS for signal amplifications after JJ is of particular interest in this case.
We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.
This paper describes the design and development of a 250W orbit average electrical power system electronic Power Node and software for use in Low Earth Orbit missions. The mass of the Power Node is 3.6 Kg (8 lb.). The dimensions of the Power Node are 30cm x 26cm x 7.9cm (11 in. x 10.25 in x 3.1 in.) The design was realized using software, Field Programmable Gate Array (FPGA) digital logic and surface mount technology. The design is generic enough to reduce the non-recurring engineering for different mission configurations. The Power Node charges one to five, low cost, 22-cell 4 AH D-cell battery packs independently. The battery charging algorithms are executed in the power software to reduce the mass and size of the power electronic. The Power Node implements a peak-power tracking algorithm using an innovative hardware/software approach. The power software task is hosted on the spacecraft processor. The power software task generates a MIL-STD-1553 command packet to update the Power Node control settings. The settings for the battery voltage and current limits, as well as minimum solar array voltage used to implement peak power tracking are contained in this packet. Several advanced topologies are used in the Power Node. These include synchronous rectification in the bus regulators, average current control in the battery chargers and quasi-resonant converters for the Field Effect Transistor (FET) transistor drive electronics. Lastly, the main bus regulator uses a feed-forward topology with the PWM implemented in an FPGA.
Extremely high sensitivity detectors, such as silicon bolometers are required in many NASA missions for detection of photons from the x-ray to the far infrared regions. Typically, these detectors are cooled to well below the liquid helium (LHe) temperature (4.2 K) to achieve the maximum detection performance. As photoconductors, they are generally operated with a load resistor and a pre-set bias voltage, which is then coupled to the input gate of a source-follower Field Effect Transistor (FET) circuit. It is imperative that the detector system signal to noise performance be limited by the noise of the detector and not by the noise of the external components. The load resistor value is selected to optimize the detector performance. These two criteria tend to be contradictory in that these detectors require load resistors in the hundreds of megaohms, which leads to a higher Johnson noise. Additionally, the physical size of the resistor must be small for device integration as required by such missions as the NASA High Resolution Airborne Wide-Band Camera (HAWC) instrument and the Submillimeter High Angular Resolution Camera (SHARC) for the Caltech Submillimeter Observatory (CSO). We have designed, fabricated and characterized thin film resistors using a CrSi/TiW/Al metal system on optical quality quartz substrates. The resistor values range from 100 megaohms to over 650 megaohms and are Johnson noise limited at LHe temperatures. The resistor film is sputtered with a sheet resistance ranging from 300 ohms to 1600 ohms and the processing sequence developed for these devices allows for chemically fine tuning the sheet resistance in-situ. The wafer fabrication process was of sufficiently high yield (>80%) providing clusters of good resistors for integrated multiple detector channels, a very important feature in the assembly of these two instruments.
The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.