Search NASA⌕ Search

SEARCH · Search NASA

Results for “gate”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Primitive quantum gates for an S U ( 3 ) discrete subgroup: Σ ( 36 × 3 )

We construct the primitive gate set for the digital quantum simulation of the 108-element Σ ( 36 × 3 ) group. This is the first time a non-Abelian crystal-like subgroup of S U ( 3 ) has been constructed for quantum simulation. The gauge link registers and necessary primitives—the inversion gate, the group multiplication gate, the trace gate, and the Σ ( 36 × 3 ) Fourier transform—are presented for both an eight-qubit encoding and a heterogeneous three-qutrit plus two-qubit register. For the latter, a specialized compiler was developed for decomposing arbitrary unitaries onto this architecture. Published by the American Physical Society 2024

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Learning Quantum States and Unitaries of Bounded Gate Complexity

While quantum state tomography is notoriously hard, most states hold little interest to practically minded tomographers. Given that states and unitaries appearing in nature are of bounded gate complexity, it is natural to ask if efficient learning becomes possible. In this work, we prove that to learn a state generated by a quantum circuit with G two-qubit gates to a small trace distance, a sample complexity scaling linearly in G is necessary and sufficient. We also prove that the optimal query complexity to learn a unitary generated by G gates to a small average-case error scales linearly in G . While sample-efficient learning can be achieved, we show that under reasonable cryptographic conjectures, the computational complexity for learning states and unitaries of gate complexity G must scale exponentially in G . We illustrate how these results establish fundamental limitations on the expressivity of quantum machine-learning models and provide new perspectives on no-free-lunch theorems in unitary learning. Together, our results answer how the complexity of learning quantum states and unitaries relate to the complexity of creating these states and unitaries. Published by the American Physical Society 2024

Zhao, Haimeng (ORCID:0000000166751489)↗
DOE OSTI2025

Realization and Calibration of Continuously Parameterized Two-Qubit Gates on a Trapped-Ion Quantum Processor

Continuously parameterized two-qubit gates are a key feature of state-of-the-art trapped-ion quantum processors, as they have favorable error scalings and show distinct improvements in circuit performance over more restricted maximally entangling gatesets. In this work, we provide a comprehensive and pedagogical discussion on how to practically implement these continuously parameterized Mølmer–Sørensen gates on the Quantum Scientific Computing Open User Testbed, a low-level trapped-ion processor. To generate the arbitrary entangling angles, θ, we simply scale the amplitude of light used to generate the entanglement. However, doing so requires careful consideration of amplifier saturation as well as the variable light shifts that result. As such, we describe a method to calibrate and cancel the dominant fourth-order effects, followed by a dynamic virtual phase advance during the gate to cancel any residual light shifts, and find a linear scaling between θ and the residual light shift. Once we have considered and calibrated these effects, we demonstrate performance improvement with decreasing θ. Finally, we describe nuances of hardware control to transform the XX-type interaction of the arbitrary-angle Mølmer–Sørensen gate into a phase-agnostic and crosstalk-mitigating ZZ interaction.

Yale, Christopher Gordon [Sandia National Laborato↗
DOE OSTI2025

Fast and High-Fidelity SNAP Gate Enabled by Optimal Control on Floquet-Engineered Systems

Superconducting cavities with high quality factors, coupled to nonlinear ancilla, provide a promising platform for quantum information storage and manipulation. However, the commonly used selective number-dependent arbitrary phase (SNAP) gate faces significant challenges in ultra-high-coherence cavities, where weak dispersive shifts result in prolonged gate times. Here, we propose a protocol to achieve high-fidelity SNAP gates that are orders of magnitude faster than the standard implementation, breaking the speed limit set by the bare dispersive shift. This enhancement is achieved by dynamically amplifying dispersive coupling via sideband interactions, followed by quantum optimal control on Floquet-engineered systems. Additionally, we present a unified perturbation theory that explains both the gate acceleration and associated benign drive-induced decoherence, corroborated by Floquet\textendash Markov simulations. These results pave the way for the experimental realization of high-fidelity control of weakly coupled, high-coherence cavities, and expanding the scope of optimal control techniques in Floquet quantum systems.

You, Xinyuan [Fermilab]↗
DOE OSTI2025

Rapid Inference of Logic Gate Neural Networks for Anomaly Detection in High Energy Physics

The increasing data rates and complexity of detectors at the Large Hadron Collider (LHC) necessitate fast and efficient machine learning models, particularly for rapid selection of what data to store, known as triggering. Building on recent work in differentiable logic gates, we present a public implementation of a Convolutional Differentiable Logic Gate Neural Network (CLGN). We apply this to detecting anomalies at the Level-1 Trigger at CMS using public data from the CICADA project. We demonstrate that the CLGN achieves physics performance on par with or superior to conventional quantized neural networks. We also synthesize an LGN for a Field-Programmable Gate Array (FPGA) and show highly promising FPGA characteristics, notably zero Digital Signal Processor (DSP) resource usage. This work highlights the potential of logic gate networks for high-speed, on-detector inference in High Energy Physics and beyond.

FOS: Physical sciences↗
NASA NTRS1972

High voltage and current, gate assisted, turn-off thyristor development

An improved high speed power switch with unique turn-off capability was developed. This gate assisted turn-off thyristor (GATT) was rated 1000 volts and 100 amperes with turn-off times of 2 microseconds. Fifty units were delivered for evaluation. In addition, test circuits designed to relate to the series inverter application were built and demonstrated. In the course of this work it was determined that the basic device design is adequate to meet the static characteristics and dynamic turn-off specification. It was further determined that the turn-on specification is critically dependent on the gate drive circuit due to the distributive nature of the cathode-gate geometry. Future work should emphasize design modifications which reduce the gate current required for fast turn-on, thereby opening the way to higher power (current) devices.

Nowalk, T. P.↗
NASA NTRS1975

Development of a 1000V, 200A, low-loss, fast-switching, gate-assisted turn-off thyristor

Feasibility was demonstrated for a thyristor that blocks 1000V forward and reverse, conducts 200A, and turns on in little more than 2 microsec with only 2A of gate drive. Its features include a turn-off time of 3 microsec achieved with 2A of gate assist current of a few microseconds duration and an energy dissipation of only 12 mJ per pulse for a 20 microsec half sine wave, 200A pulse. Extensive theoretical and experimental study of the electrical behavior of thyristors having a fast turn-off time have significantly improved the understanding of the physics of turning thyristor off. Thyristors of two new designs were fabricated and evaluated. The high speed and low power were achieved by a combination of gate amplification, cathode shunting, and gate-assisted turn-off. Two techniques for making this combination practical are described.

Schlegel, E. S.↗
NASA NTRS1981

Reliability study of refractory gate gallium arsenide MESFETS

Refractory gate MESFET's were fabricated as an alternative to aluminum gate devices, which have been found to be unreliable as RF power amplifiers. In order to determine the reliability of the new structures, statistics of failure and information about mechanisms of failure in refractory gate MESFET's are given. Test transistors were stressed under conditions of high temperature and forward gate current to enhance failure. Results of work at 150 C and 275 C are reported.

Yin, J. C. W.↗
NASA NTRS1991

Stacked-Gate FET's For Analog Memory Elements

Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

Thakoor, Anilkumar P.↗
NASA NTRS1992

An analysis of the temperature dependence of the gate current in complementary heterojunction field-effect transistors

The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.

Cunningham, Thomas J.↗
NASA NTRS1993

Effect of trapped ions in a gated time-of-flight apparatus

A three-mesh gate is used in a time-of-flight (TOF) apparatus to analyze the velocity of positive ions. Test results and a theoretical description are presented of an effect arising from trapping ions between meshes of a two-gate TOF velocity analyzer. The entrapped ions produce a side peak in the TOF spectra corresponding to faster ions. The onset and relative height of the side peak is dependent on the gating voltage and risetime of the pulsing electronics, while the relative intensity depends upon the velocity being sampled and the ratio of the gate width to duration.

Martus, K. E.↗
NASA NTRS1993

Design of CMOS logic gates for TID radiation

The rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.

Attia, John Okyere↗
NASA NTRS2000

Detection of Objects Hidden in Highly Scattering Media Using Time-Gated Imaging Methods

Non-intrusive and non-invasive optical imaging techniques has generated great interest among researchers for their potential applications to biological study, device characterization, surface defect detection, and jet fuel dynamics. Non-linear optical parametric amplification gate (NLOPG) has been used to detect back-scattered images of objects hidden in diluted Intralipid solutions. To directly detect objects hidden in highly scattering media, the diffusive component of light needs to be sorted out from early arrived ballistic and snake photons. In an optical imaging system, images are collected in transmission or back-scattered geometry. The early arrival photons in the transmission approach, always carry the direct information of the hidden object embedded in the turbid medium. In the back-scattered approach, the result is not so forth coming. In the presence of a scattering host, the first arrival photons in back-scattered approach will be directly photons from the host material. In the presentation, NLOPG was applied to acquire time resolved back-scattered images under the phase matching condition. A time-gated amplified signal was obtained through this NLOPG process. The system's gain was approximately 100 times. The time-gate was achieved through phase matching condition where only coherent photons retain their phase. As a result, the diffusive photons, which were the primary contributor to the background, were removed. With a large dynamic range and high resolution, time-gated early light imaging has the potential for improving rocket/aircraft design by determining jets shape and particle sizes. Refinements to these techniques may enable drop size measurements in the highly scattering, optically dense region of multi-element rocket injectors. These types of measurements should greatly enhance the design of stable, and higher performing rocket engines.

Galland, Pierre A.↗
NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗
NASA NTRS1983

Frequency tracked gated pulse technique for ultrasonic frequency

A tracking generator 21 is slaved to a spectrum analyzer 23 to produce an input signal having a frequency that follows the frequency of the spectrum analyzer sweeping local oscillator 22. The input signal is gated to a transducer 26 by a transmitter gate 25 to produce ultrasonic waves in the sample 28. The resulting ultrasonic echoes are converted into electrical signals by the transducer and then gated into the spectrum analyzer by receiver gate 29. This arrangement produces spectra that are equivalent to shock-exciting the transducer with a true delta function shock-excitation.

Cantrell, Jr., John H.↗
NASA NTRS2008

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗
NASA NTRS2006

Three-Function Logic Gate Controlled by Analog Voltage

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Zebulum, Ricardo↗
NASA NTRS2003

Block QCA Fault-Tolerant Logic Gates

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA-based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

Firjany, Amir↗