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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A formalism for target fragment transport is presented with application to energy loss spectra in thin silicon devices. A nuclear data base is recommended that agrees well with the measurements of McNulty et al. using surface barrier detectors. High-energy events observed by McNulty et al., which are not predicted by intranuclear cascade models, are well represented by the present work.
Hybrid silicon Infrared Charge Coupled Devices (IRCCDs) are evaluated for use as viable astronomical detectors. A Si:In photoconductor array which is bump-bonded to a silicon multiplexer is described. A summary of the device parameters is given.
Through-silicon via (TSV) is the latest in a progression of technologies for stacking silicon devices in three dimensions (3D). Driven by the need for improved performance, methods to use short vertical interconnects to replace the long interconnects found in 2D structures have been developed. The industry is moving past the feasibility (research and development [R and D]) phase for TSV technology into the commercialization phase where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Even though design, thermal, and test issues remain, much progress has been made.
The results of the program for the development of a more sensitive method for selecting silicon planar semiconductor devices for long life applications are reported. The manufacturing technologies (MOS and Bipolar) are discussed along with the screening procedures developed as a result of the tests and evaluations, and the effectiveness of the MOS and Bilayer screening procedures are evaluated.
Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.
We study the effects of compressive and tensile biaxial strain on direct and phonon-assisted Auger–Meitner recombination (AMR) in silicon using first-principles calculations. We find that the application of strain has a non-trivial effect on the AMR rate. For most AMR processes, the application of strain increases the AMR rate. However, the recombination rate for the AMR process involving two holes and one electron is suppressed by 38% under tensile strain. We further analyze the specific phonon contributions that mediate the phonon-assisted AMR mechanism, demonstrating the increased anisotropy under strain. In conclusion, our results indicate that the application of tensile strain increases the lifetime of minority electron carriers in p-type silicon and can be leveraged to improve the efficiency of silicon devices.
Image sensors with nondestructive charge readout provide single-photon or single-electron sensitivity, but at the cost of long readout times. We present a smart readout technique to allow the use of these sensors in visible light and other applications that require faster readout times. The method optimizes the readout noise and time by changing the number of times pixels are read out either statically, by defining an arbitrary number of regions of interest in the array, or dynamically, depending on the charge or energy of interest in the pixel. This technique is tested in a Skipper CCD showing that it is possible to obtain deep subelectron noise, and therefore, high resolution of quantized charge, while dynamically changing the readout noise of the sensor. These faster, low noise readout techniques show that the skipper CCD is a competitive technology even where other technologies such as electron multiplier charge coupled devices, silicon photo multipliers, etc. are currently used. This technique could allow skipper CCDs to benefit new astronomical instruments, quantum imaging, exoplanet search and study, and quantum metrology.
Entanglement between photons and a quantum memory is a key component of quantum repeaters, which allow long-distance quantum entanglement distribution in the presence of fiber losses. Spin-photon entanglement has been implemented with a number of different atomic and solid-state qubits with long spin coherence times, but none directly emit photons into the 1.5 − μ m telecom band where losses in optical fibers are minimized. Here, we demonstrate spin-photon entanglement using a single rare earth ion in the solid-state Er 3 + coupled to a silicon nanophotonic cavity, which directly emits photons at 1532.6 nm. We infer an entanglement fidelity of 73(3)% after propagating through 15.6 km of optical fiber. This work opens the door to large-scale quantum networks based Er 3 + ions, leveraging scalable silicon device fabrication and spectral multiplexing. Published by the American Physical Society 2025
Effective thermal management of traction-drive power electronics is critical to the advancement of electric-drive vehicles and is necessary for increasing power density and improving reliability. Replacing traditional silicon devices with more efficient, higher temperature, higher voltage, and higher frequency wide-bandgap (WBG) devices will enable increased power density but will result in higher device heat fluxes. Compact packaging of high-temperature WBG devices near low-temperature-rated components creates thermal management challenges that need to be addressed for future power-dense systems. This paper summarizes the thermal performance of on-road automotive power electronics thermal management systems and provides thermal performance and pumping-power metrics for select vehicles. Thermal analyses reveal that the package/conduction resistance dominates the total thermal resistance (for existing automotive systems). We model advanced packaging concepts and compare the results with existing packaging designs to quantify their thermal performance enhancements. Double-side-cooled configurations that do not use thermal interface materials are package concepts predicted to provide a low junction-to-fluid thermal resistance (compared to current packages). Dielectric-fluid-cooled concepts enable a redesign of the package to reduce the package resistance, can be implemented in single- and two-phase cooling approaches, and allow for cooling of passive components (e.g., capacitors) and bus bars.
The Advanced Scintillator Compton Telescope (ASCOT) is a medium-energy gamma-ray Compton telescope flown on NASA’s high-altitude scientific balloon from Palestine, TX on 5th July 2018. It uses commercially available highperformance scintillators like Cerium Bromide (CeBr3) and p-terphenyl along with compact readout devices - silicon photomultipliers (SiPMs) - for an improved instrument response. ASCOT was built to address the existing need for observations in the gamma-ray energy range of 0.4 - 20 MeV. Operating stably throughout the mission, it reached an altitude of 120,000 ft and observed the Crab Nebula at MeV energies for ~5 hours. Built on the legacy of COMPTEL (onboard CGRO), along with the hardware advancement ASCOT also makes use of the Time-of-Flight (ToF) background rejection technique for effective imaging. Presented here is the Energy and ToF calibrated flight data with optimal data cuts (Earth Horizon Cut, Pulse Shape Discrimination Cut). The growth curves generated using this data from 5 to 100 g/cm2 of residual atmosphere in conjunction with the Monte Carlo simulations of the instrument response have been used to obtain the Cosmic Diffuse Gamma-ray (CDG) flux value of (1.28 ± 0.37)×10 -5 photons/cm 2 /s/sr/keV for 0.4 – 0.7 MeV energy range. The 3σ upper limit for CDG flux is 1.8×10-5 photons/cm 2 /s/sr/keV for 0.7-1.5 MeV and 2×10-6 photons/cm2/s/sr/keV for 1.5-2.5 MeV. The analysis of the Crab Nebula from flight observation is underway
The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.
Auger electron spectroscopy, surface contamination, and silicon device parameters for microcircuits
Book on integrated circuits and semiconductor devices covering MOSFET, optoelectronic devices, silicon controlled rectifiers and thyristors
Totally depleted silicon diodes are discussed which are used as nuclear particle detectors in investigations of galactic and solar cosmic radiation and trapped radiation. A study of radiation and chemical effects on the diodes was conducted. Work on electron and proton irradiation of surface barrier detectors with thicknesses up to 1 mm was completed, and work on lithium-drifted silicon devices with thicknesses of several millimeters was begun.
Critical reappraisal of the bias dependence of the dc and small-signal ac current gain factors of planar bipolar transistors over a wide range of currents. This is based on a straightforward consideration of the three basic components of the dc base current arising due to emitter-to-base injected minority carrier transport, base-to-emitter carrier injection, and emitter-base surface depletion layer recombination effects. Experimental results on representative n-p-n and p-n-p silicon devices are given which support most of the analytical findings.
The white noise level of space-charge-limited current (SCLC) of holes in a silicon device measured at five temperatures ranging from 113 to 300 K is shown to be proportional to the absolute temperature. This proves experimentally the thermal origin of noise for SCLC in solids.
Silicon pn junction solar cells made with low-resistivity substrates show poorer performance than traditional theory predicts. The purpose of this research was to identify and characterize the physical mechanisms responsible for the discrepancy. Attention was concentrated on the open circuit voltage in shallow junction cells of 0.1 ohm-cm substrate resistivity. A number of possible mechanisms that can occur in silicon devices were considered. Two mechanisms which are likely to be of main importance in explaining the observed low values of open-circuit voltage were found: (1) recombination losses associated with defects introduced during junction formation, and (2) inhomogeneity of defects and impurities across the area of the cell. To explore these theoretical anticipations, various diode test structures were designed and fabricated and measurement configurations for characterizing the defect properties and the areal inhomogeneity were constructed.