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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 91 records · Page 5
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

The GREEN ‘omics of Nutrient Feedbacks to Soil Warming

The GREEN ‘omics of Nutrient Feedbacks in Soil project advanced the DOE Biological and Environmental Research (BER) mission by developing and applying isotope-enabled ’omics tools to understand how soil microbes regulate carbon and nutrient cycling. Guided by the Growth Rate, growth Efficiency, and stoichiometry of Essential Nutrients (GREEN ’omics) framework, the project aimed to build a predictive, systems-level understanding of microbial traits that control ecosystem biogeochemistry. In a collaboration among Northern Arizona University (lead), West Virginia University, Lawrence Livermore National Laboratory, and Pacific Northwest National Laboratory, we combined quantitative stable isotope probing (qSIP), Chip-SIP, NanoSIMS, and genome-resolved metagenomics across long-term experiments in Arctic, boreal, temperate, and tropical ecosystems. The project produced three key outcomes: 1) We showed that community-weighted temperature sensitivities of bacterial growth (Q10) can predict ecosystem-scale soil respiration responses across diverse soils. 2) We provided the first in situ evidence for density-dependent population dynamics in soil bacteria and demonstrated that nutrient additions intensify competition, concentrating carbon use into fewer taxa. 3) We improved and extended isotope-enabled ’omics methods by quantifying qSIP measurement error to guide experimental design and coupling SIP with genome-resolved metagenomics to reveal cross-kingdom interactions among bacteria, fungi, and viruses. Together, these results show that a small number of microbial traits and taxa exert disproportionate control over soil carbon and nutrient cycling, providing critical data and methods to improve representation of microbial processes in Earth system models.

54 ENVIRONMENTAL SCIENCES↗
NASA NTRS1986

A systolic architecture for the correlation and accumulation of digital sequences

A fully systolic architecture for the implementation of digital sequence correlator/accumulators is described. These devices consist of a two-dimensional array of processing elements that are conceived for efficient fabrication in Very Large Scale Integrated (VLSI) circuits. A custom VLSI chip that was implemented using these concepts is described. The chip, which contains a four-lag three-level sequence correlator and four bits of accumulation with overflow detection, was designed using the Integrated UNIX-Based Computer Aided Design (CAD) System. Applications of such devices include the synchronization of coded telemetry data, alignment of both real time and non-real time Very Large Baseline Interferometry (VLBI) signals, and the implementation of digital filters and processes of many types.

Deutsch, L. J.↗
NASA NTRS1991

Programmable digital modem

The design of the Programmable Digital Modem (PDM) is outlined. The PDM will be capable of operating with numerous modulation techniques including: 2-, 4-, 8- and 16-ary phase shift keying (PSK), minimum shift keying (MSK), and 16-ary quadrature amplitude modulation (QAM), with spectral occupancy from 1.2x to 2x the data symbol rate. It will also be programmable for transmission rates ranging from 2.34 to 300 Mbit/s, where the maximum symbol rate is 75 Msymbol/s. Furthermore, these parameters will be executable in independent burst, dependent burst, or continuous mode. In dependent burst mode the carrier and clock oscillator sources are common from burst to burst. To achieve as broad a set of requirements as these, it is clear that the essential signal processing must be digital. In addition, to avoid hardware changes when the operational parameters are changed, a fixed interface to an analog intermediate frequency (IF) is necessary for transmission; and, common system level architectures are necessary for the modulator and demodulator. Lastly, to minimize size and power, as much of the design as possible will be implemented with application specific integrated circuit (ASIC) chips.

Poklemba, John J.↗
NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗
NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗
NASA NTRS1990

FEC decoder design optimization for mobile satellite communications

A new telecommunications service for location determination via satellite is being proposed for the continental USA and Europe, which provides users with the capability to find the location of, and communicate from, a moving vehicle to a central hub and vice versa. This communications system is expected to operate in an extremely noisy channel in the presence of fading. In order to achieve high levels of data integrity, it is essential to employ forward error correcting (FEC) encoding and decoding techniques in such mobile satellite systems. A constraint length k = 7 FEC decoder has been implemented in a single chip for such systems. The single chip implementation of the maximum likelihood decoder helps to minimize the cost, size, and power consumption, and improves the bit error rate (BER) performance of the mobile earth terminal (MET).

Roy, Ashim↗
NASA NTRS1976

CMOS array design automation techniques

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Lombardi, T.↗
NASA NTRS1995

Averting Denver Airports on a Chip

As a result of recent advances in software engineering capabilities, we are now in a more stable environment. De-facto hardware and software standards are emerging. Work on software architecture and design patterns signals a consensus on the importance of early system-level design decisions, and agreements on the uses of certain paradigmatic software structures. We now routinely build systems that would have been risky or infeasible a few years ago. Unfortunately, technological developments threaten to destabilize software design again. Systems designed around novel computing and peripheral devices will spark ambitious new projects that will stress current software design and engineering capabilities. Micro-electro-mechanical systems (MEMS) and related technologies provide the physical basis for new systems with the potential to produce this kind of destabilizing effect. One important response to anticipated software engineering and design difficulties is carefully directed engineering-scientific research. Two specific problems meriting substantial research attention are: A lack of sufficient means to build software systems by generating, extending, specializing, and integrating large-scale reusable components; and a lack of adequate computational and analytic tools to extend and aid engineers in maintaining intellectual control over complex software designs.

Sullivan, Kevin J.↗
DOE OSTI2024

DIRECT RF SAMPLING BASED LLRF CONTROL SYSTEM FOR C-BAND LINEAR ACCELERATOR

Low Level RF (LLRF) control systems of linear accel- erators (LINACs) are typically implemented with hetero- dyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Fre- quency System-on-Chip (RFSoC) device from AMD Xilinx integrates data converters with maximum RF frequency of 6 GHz. This enables direct RF sampling of C-band LLRF signal typically operated at 5.712 GHz without any analogue mixers, which can significantly simplify the system architec- ture. The data converters sample RF signals in higher order Nyquist zones and then up or down convert digitally by the integrated data path in RFSoC. The closed-loop feedback control firmware implemented in FPGA integrated in RF- SoC can process the base-band signal from the ADC data path and calculate the updated phase and amplitude to be up- mixed by the DAC data path. We have developed a C-band LLRF control RFSoC platform with direct RF sampling, which targets Cool Copper Collider (𝐶3) and other C or S band LINAC research and development projects. In this paper, the architecture of the platform will be described. We have optimized the configuration of the data converter and characterized performance of them with RF pulses. The test results for some of the key performance parameters for the LLRF platform with our custom solid-state amplifier, such as phase and amplitude stability, will be discussed in this paper.

Liu, C↗
NASA NTRS2010

Evaluation of Fairchild's Gate Drive Optocoupler, Type FOD3150, Under Wide Temperature Operation

An optocoupler is a semiconductor device that is used to transfer a signal between different parts of a circuit that need to be electrically isolated from one another - for example, where a high voltage is to be switched with a low voltage control signal. Optocouplers often can be used in place of relays. These optocouplers utilize an infrared LED (light emitting diode) and a photodetector such as a silicon controlled rectifier or photosensitive silicon diode for the transfer of the electronic signal between components of a circuit by means of a short optical transmission channel. For maximum coupling, the wave-length responses of the LED and the detector should be very similar. In switch-mode power supply applications, optocouplers offer advantages over transformers by virtue of simpler circuit design, reduced weight, and DC coupling capability. The effects of extreme temperature exposure and thermal cycling on the performance of a commercial-off-the-shelf (COTS) optocoupler, Fairchild FOD3150, were evaluated in this work. This 1.0 A output current, high noise immunity gate drive optocoupler utilizes an aluminum gallium arsenide (AlGaAs) LED, is capable of driving most 800V/20A IGBT/MOSFETs, and is suited for fast switching in motor control inverter applications and high performance power systems. Some of the specifications of the isolator chip are listed. The device was evaluated in terms of output response, output rise (t(sub r)) and fall times (t(sub f)), and propagation delays (using a 50% level between input and output during low to high (t(sub PLH)) and high to low (t(sub PLH)) transitions). The output supply current was also obtained. These parameters were recorded at various test temperatures between -190 C and +110 C.

Patterson, Richard↗
DOE OSTI2025

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems

Domain-specific systems improve the performance of a specific set of applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration to optimize the compute performance of the generated accelerators. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how the accelerators access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization on average by 53.2% for a set of PolyBench kernels.

Limaye, Ankur M. (ORCID:0000000194062584)↗
NASA NTRS1983

Some methods of estimating a coverage parameter

To demonstrate the high reliability of fault-tolerant computing systems, experimental testing can be performed by injecting faults into their hardware and observing the times needed to detect and isolate failed components and reconfigure the good components. Coverage, a parameter measuring continued system success, is the probability that recovery occurs before other, perhaps catastrophic, component failures occur. Methods of estimating coverage are given for the case of randomly selecting a subset of the pins or chips for testing. Pin-level samples of times to recovery are treated by the Type I censoring model often used in life testing.

Lee, L. D.↗
NASA NTRS1993

Towards the formal verification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the Higher-Order Logic (HOL) listings of the partial verification of the requirements and design for a commercially developed processor interface unit (PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault tolerant computer system. This system, the Fault Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU verification as it currently exists. Section two of this report contains general-purpose HOL theories and definitions that support the PIU verification. These include arithmetic theories dealing with inequalities and associativity, and a collection of tactics used in the PIU proofs. Section three contains the HOL listings for the completed PIU design verification. Section 4 contains the HOL listings for the partial requirements verification of the P-Port.

Fura, David A.↗
NASA NTRS2003

Low-Power SOI CMOS Transceiver

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

Fujikawa, Gene↗
DOE OSTI2026

Fine-Grained Power and Energy Attribution on AMD GPU/APU-Based Exascale Nodes

Modern exascale GPU- and APU-based systems provide multiple power and energy sensors, but differences in scope, update rate, timing, and filtering complicate the attribution of short-lived accelerator activity. This paper presents a methodology to characterize and correct these effects on Cray EX systems with AMD Instinct MI250X GPUs (Frontier) and MI300A APUs (Portage). Using controlled square-wave workloads, we quantify update intervals, delay, aliasing, and variability across up to 512 GPUs and 480 APUs with on-chip (rocm-smi/amd-smi) and off-chip Cray Power Management sensors. We reconstruct power from cumulative energy counters to achieve faster response times, validate it against on-chip, off-chip, and node-level sensors, and integrate the resulting streams into a Score-P/PAPI-based tool for time-aligned, phase-level attribution. Applied to rocHPL, rocHPL-MxP, and HPG-MxP, the method separates energy savings due to reduced runtime from changes in power. Mixed precision reduces node energy on Frontier by 79% for rocHPL-MxP and 31% for HPG-MxP, with similar trends on Portage. These results provide portable guidance for sensor validation and power-aware optimization on current and future exascale systems.

Mcdaniel, Adam [ORNL] (ORCID:000000016926028X)↗
NASA NTRS1993

Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.

Fura, David A.↗
NASA NTRS2008

Advanced Land Imager Assessment System

The Advanced Land Imager Assessment System (ALIAS) supports radiometric and geometric image processing for the Advanced Land Imager (ALI) instrument onboard NASA s Earth Observing-1 (EO-1) satellite. ALIAS consists of two processing subsystems for radiometric and geometric processing of the ALI s multispectral imagery. The radiometric processing subsystem characterizes and corrects, where possible, radiometric qualities including: coherent, impulse; and random noise; signal-to-noise ratios (SNRs); detector operability; gain; bias; saturation levels; striping and banding; and the stability of detector performance. The geometric processing subsystem and analysis capabilities support sensor alignment calibrations, sensor chip assembly (SCA)-to-SCA alignments and band-to-band alignment; and perform geodetic accuracy assessments, modulation transfer function (MTF) characterizations, and image-to-image characterizations. ALIAS also characterizes and corrects band-toband registration, and performs systematic precision and terrain correction of ALI images. This system can geometrically correct, and automatically mosaic, the SCA image strips into a seamless, map-projected image. This system provides a large database, which enables bulk trending for all ALI image data and significant instrument telemetry. Bulk trending consists of two functions: Housekeeping Processing and Bulk Radiometric Processing. The Housekeeping function pulls telemetry and temperature information from the instrument housekeeping files and writes this information to a database for trending. The Bulk Radiometric Processing function writes statistical information from the dark data acquired before and after the Earth imagery and the lamp data to the database for trending. This allows for multi-scene statistical analyses.

Chander, Gyanesh↗
NASA NTRS1990

Numerical analysis of bipropellant combustion in orbit maneuvering vehicle thrust chamber

The combustion and aerodynamic processes of liquid-liquid bipropellant; monomethylhydrazine and nitrogen tetroxide in the combustion chamber of a variable thrust engine (VTE) have been examined to assess the flow structure, combustion characteristics, and wall heat transfer under the simulated engine operations at two power levels. The Generalized Elliptic Multi-phase flow with Chemical reaction, Heat transfer and Interfacial Processes (GEM-CHIP) code and the Bipropellant Combustion (BICOMB) code, which is the GEMCHIP algorithm reformulated in the frame work of a body fitted coordinate system, have been used for the numerical study. Combustion flow structure with non-premixed type injection that simulates the impingement type injector is predicted and the results are compared with that of the premixed injector.

Chiu, H. H.↗