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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 919 records · Page 51
All sourcesNASA NTRSDOE OSTI
NASA NTRS1999

Experiments on Evolving Software Models of Analog Circuits

Analog circuits are of great importance in electronic system design since the world is fundamentally analog in nature. While the amount of digital design activity far outpaces that of analog design, most digital systems require analog modules for interfacing with the external world. It was recently estimated that approximately 60% of digital application- specific integrated circuit designs incorporated analog circuits. With challenging analog circuit design problems and few analog design engineers, there are economic reasons for automating the analog design process, especially time-to-market considerations. Techniques for analog circuit design automation began appearing about two decades ago. These methods incorporated heuristics [6], knowledge bases [1], simulated annealing [5], and other algorithms. Efforts using techniques from evolutionary computation began appearing over the last few years. These include the use of genetic algorithms to select electronic component values (for example, the resistance value of a resistor), to select circuit topologies, and to design amplifiers using a limited set of canned topologies [4]. A genetic programming-based analog circuit design system has been demonstrated in which the circuit sizes, component values, and the circuit topologies are determined automatically [3]. The genetic-algorithm systems typically represent circuit structures as vectors of parameters encoded in binary strings, while the genetic programming system manipulates tree data structures.

Lohn, Jason D.↗
NASA NTRS2013

An Offload NIC for NASA, NLR, and Grid Computing

This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems, and to add several more capabilities while reducing space consumption and cost. Provisions were designed for interoperability with systems used in the NASA HEC (High-End Computing) program. The new acceleration engine consists of state-ofthe- art FPGA (field-programmable gate array) core IP, C, and Verilog code; novel communication protocol; and extensions to the Globus structure. The engine provides the functions of network acceleration, encryption, compression, packet-ordering, and security added to Globus grid or for cloud data transfer. This system is scalable in nX10-Gbps increments through 100-Gbps f-d. It can be interfaced to industry-standard system-side or network-side devices or core IP in increments of 10 GigE, scaling to provide IEEE 40/100 GigE compliance.

Awrach, James↗
NASA NTRS2013

Small Projects Rapid Integration and Test Environment (SPRITE): Application for Increasing Robutness

Over the past few years interest in the development and use of small satellites has rapidly gained momentum with universities, commercial, and government organizations. In a few years we may see networked clusters of dozens or even hundreds of small, cheap, easily replaceable satellites working together in place of the large, expensive and difficult-to-replace satellites now in orbit. Standards based satellite buses and deployment mechanisms, such as the CubeSat and Poly Pico-satellite Orbital Deployer (P-POD), have stimulated growth in this area. The use of small satellites is also proving to be a cost effective capability in many areas traditionally dominated by large satellites, though many challenges remain. Currently many of these small satellites undergo very little testing prior to flight. As these small satellites move from technology demonstration and student projects toward more complex operational assets, it is expected that the standards for verification and validation will increase.

Lee, Ashley↗
NASA NTRS2013

Remote Memory Access Protocol Target Node Intellectual Property

The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

Haddad, Omar↗
NASA NTRS2014

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗
NASA NTRS2013

The Effect of Fiber Strength Stochastics and Local Fiber Volume Fraction on Multiscale Progressive Failure of Composites

Continuous fiber unidirectional polymer matrix composites (PMCs) can exhibit significant local variations in fiber volume fraction as a result of processing conditions that can lead to further local differences in material properties and failure behavior. In this work, the coupled effects of both local variations in fiber volume fraction and the empirically-based statistical distribution of fiber strengths on the predicted longitudinal modulus and local tensile strength of a unidirectional AS4 carbon fiber/ Hercules 3502 epoxy composite were investigated using the special purpose NASA Micromechanics Analysis Code with Generalized Method of Cells (MAC/GMC); local effective composite properties were obtained by homogenizing the material behavior over repeating units cells (RUCs). The predicted effective longitudinal modulus was relatively insensitive to small (~8%) variations in local fiber volume fraction. The composite tensile strength, however, was highly dependent on the local distribution in fiber strengths. The RUC-averaged constitutive response can be used to characterize lower length scale material behavior within a multiscale analysis framework that couples the NASA code FEAMAC and the ABAQUS finite element solver. Such an approach can be effectively used to analyze the progressive failure of PMC structures whose failure initiates at the RUC level. Consideration of the effect of local variations in constituent properties and morphologies on progressive failure of PMCs is a central aspect of the application of Integrated Computational Materials Engineering (ICME) principles for composite materials.

multiscale analysis↗
NASA NTRS2014

The Radiation, Interplanetary Shocks, and Coronal Sources (RISCS) Toolset

The goal of this project is to serve the needs of space system designers and operators by developing an interplanetary radiation environment model within 10 AU:Radiation, Interplanetary Shocks, and Coronal Sources (RISCS) toolset: (1) The RISCS toolset will provide specific reference environments for space system designers and nowcasting and forecasting capabilities for space system operators; (2) We envision the RISCS toolset providing the spatial and temporal radiation environment external to the Earth's (and other planets') magnetosphere, as well as possessing the modularity to integrate separate applications (apps) that can map to specific magnetosphere locations and/or perform the subsequent radiation transport and dosimetry for a specific target.

Zank, G. P.↗
NASA NTRS2014

Networked Operations of Hybrid Radio Optical Communications Satellites

In order to address the increasing communications needs of modern equipment in space, and to address the increasing number of objects in space, NASA is demonstrating the potential capability of optical communications for both deep space and near-Earth applications. The Integrated Radio Optical Communications (iROC) is a hybrid communications system that capitalizes on the best of both the optical and RF domains while using each technology to compensate for the other's shortcomings. Specifically, the data rates of the optical links can be higher than their RF counterparts, whereas the RF links have greater link availability. The focus of this paper is twofold: to consider the operations of one or more iROC nodes from a networking point of view, and to suggest specific areas of research to further the field. We consider the utility of Disruption Tolerant Networking (DTN) and the Virtual Mission Operation Center (VMOC) model.

Delay Tolerant Networking↗
NASA NTRS2016

An Efficient, FPGA-Based, Cluster Detection Algorithm Implementation for a Strip Detector Readout System in a Time Projection Chamber Polarimeter

A fundamental challenge in a spaceborne application of a gas-based Time Projection Chamber (TPC) for observation of X-ray polarization is handling the large amount of data collected. The TPC polarimeter described uses the APV-25 Application Specific Integrated Circuit (ASIC) to readout a strip detector. Two dimensional photoelectron track images are created with a time projection technique and used to determine the polarization of the incident X-rays. The detector produces a 128x30 pixel image per photon interaction with each pixel registering 12 bits of collected charge. This creates challenging requirements for data storage and downlink bandwidth with only a modest incidence of photons and can have a significant impact on the overall mission cost. An approach is described for locating and isolating the photoelectron track within the detector image, yielding a much smaller data product, typically between 8x8 pixels and 20x20 pixels. This approach is implemented using a Microsemi RT-ProASIC3-3000 Field-Programmable Gate Array (FPGA), clocked at 20 MHz and utilizing 10.7k logic gates (14% of FPGA), 20 Block RAMs (17% of FPGA), and no external RAM. Results will be presented, demonstrating successful photoelectron track cluster detection with minimal impact to detector dead-time.

Polarimeter↗
NASA NTRS2015

Data Concentrator

Orbital Research, Inc., developed, built, and tested three high-temperature components for use in the design of a data concentrator module in distributed turbine engine control. The concentrator receives analog and digital signals related to turbine engine control and communicates with a full authority digital engine control (FADEC) or high-level command processor. This data concentrator follows the Distributed Engine Controls Working Group (DECWG) roadmap for turbine engine distributed controls communication development that operates at temperatures at least up to 225 C. In Phase I, Orbital Research developed detailed specifications for each component needed for the system and defined the total system specifications. This entailed a combination of system design, compiling existing component specifications, laboratory testing, and simulation. The results showed the feasibility of the data concentrator. Phase II of this project focused on three key objectives. The first objective was to update the data concentrator design modifications from DECWG and prime contractors. Secondly, the project defined requirements for the three new high-temperature, application-specific integrated circuits (ASICs): one-time programmable (OTP), transient voltage suppression (TVS), and 3.3V. Finally, the project validated each design by testing over temperature and under load.

Willett, Mike↗
NASA NTRS2016

Development and Performance of a Suprathermal Electron Spectrometer to Study Auroral Precipitations

The design, development, and performance of Medium-energy Electron SPectrometer (MESP), dedicated to the in situ observation of suprathermal electrons in the auroral ionosphere, are summarized in this paper. MESP employs a permanent magnet filter with a light tight structure to select electrons with proper energies guided to the detectors. A combination of two avalanche photodiodes and a large area solid-state detector (SSD) provided 46 total energy bins (1 keV resolution for 3-20 keV range for APDs, and 7 keV resolution for greater than 20 keV range for SSDs). Multi-channel ultra-low power application-specific integrated circuits are also verified for the flight operation to read-out and analyze the detector signals. MESP was launched from Poker F1at Research Range on 3 March 2014 as a part of ground-to-rocket electrodynamics-electrons correlative experiment (GREECE) mission. MESP successfully measured the precipitating electrons from 3 to 120 keV in 120-ms time resolution and characterized the features of suprathermal distributions associated with auroral arcs throughout the flight. The measured electrons were showing the inverted-V type spectra, consistent with the past measurements. In addition, investigations of the suprathermal electron population indicated the existence of the energetic non-thermal distribution corresponding to the brightest aurora.

Ogasawara, Keiichi↗
NASA NTRS2016

A Low-Power Correlator ASIC for Arrays with Many Antennas

We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

radio telescopes↗
NASA NTRS2017

A Compact, Multi-view Net Flux Radiometer for Future Uranus and Neptune Probes

A Net Flux Radiometer (NFR) is presented that can be included in an atmospheric structure instrument suite for future probe missions to the icy giants Uranus and Neptune. The baseline design has two spectral channels i.e., a solar channel (0.4-to-3.5 m) and a thermal channel (4-to-300 m). The NFR is capable of viewing five distinct viewing angles during the descent. Non-imaging Winston cones with band-pass filters are used for each spectral channel and to define a 5 angular acceptance. Uncooled thermopile detectors are used in each spectral channel and are read out using a custom radiation hard application specific integrated circuit (ASIC). The baseline design can easily be changed to increase the number of detector channels from two to seven.

Aslam, S.↗
NASA NTRSDate not supplied

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗
NASA NTRSDate not supplied

Analysis of Historical International Space Station Logistical Mass Delivery

Crewed space exploration missions are extremely logistics dependent, as cargo requirements shape numerous program elements such as vehicle and habitat size. Logistics mass is the mass of items like food and clothing that are not a part of the vehicle or habitat, yet are required by the crew to complete the mission. Numerous studies, such as the Human Exploration Research Analog (HERA) and the Human Exploration Spacecraft Testbed for Integration and Advancement (HESTIA) 20-foot chamber analog, have been conceived to research the rates at which crews consume logistics mass. These analogs can simulate many aspects of life in space, including confinement, isolation, limited supplies, and, in certain experiments, the habitat pressure. However, some aspects of space exploration, such as the effects of low gravity and the use of space-based amenities, cannot currently be tested on the ground. In this paper, International Space Station (ISS) manifest data obtained through the National Aeronautics and Space Administration’s (NASA’s) Mission Integration Database Application System (MIDAS) portal is used as a precursor to space-based analogs. The objective of the analysis is determining the breakdown of logistics mass used in space exploration. This identifies potential areas of improvement and highlights the rates at which significant items are supplied, aiding in the weighing of alternative options such as utilizing in space manufacturing for supplies vs. manifesting spares, or cleaning clothing in flight vs. discarding it. Official flight manifests ranging a span of 878 days, just short of the three-year length of a potential human mission to Mars, were analyzed to find the rates at which astronauts consumed various logistics supplies. From this analysis we have found that contrary to our own hypothesis, ‘food’ was not the largest portion of the supplied mass. Instead, ‘Environmental Control and Life Support Systems’ (ECLSS) contributed 34% of the overall supplied mass, followed by ‘Science and Outfitting,’ which contributed 29%. Food totaled less than a quarter (21% of the resupplied mass, while other items of focus in mass reduction efforts such as ‘Hygiene’ (6%), ‘Clothing’ (3%), and ‘Operational Supplies’ (4%) each contributed less than a tenth of the supplied mass. This data suggests that by categorizing and analyzing the data based on an alternative taxonomy and analyzing the full supply manifests rather than handpicked items, we have revealed unexpectedly significant items which had not been previously tracked by exploration logistics efforts. For example, toilet hardware made up 4% of ECLSS mass, and laptop hardware and multi-tools each made up 10% of operational supplies mass. Additionally, the ‘Specialized Clothing’ subcategory containing fire protective equipment, coveralls, and penguin suits made up 15% of the overall clothing mass. By identifying these newly found significant items, we can create more realistic mass estimates for exploration missions and direct mass reduction efforts to new areas, potentially leading to lower future mission masses.

Logistics↗