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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 955 records · Page 53

Heavy Ion Testing at the Galactic Cosmic Ray Energy Peak

A 1 GeV/u 5 6Fe ion beam allows for true 90deg tilt irradiations of various microelectronic c-0mponents and reveals relevant upset trends at the GCR Hux energy peak. Three SRAMs and an SRAM-based FPGA evaluated at the NASA Space Radiation Effects Laboratory demonstrate that a 90deg tilt irradiation yields a unique device response. These tilt angle effects need t-0 be screened for, and if found, pursued with radiation transport simulations to quantify their impact on event rate calculations.

Pellish, Jonathan A.↗

A Comparison of High-Energy Electron and Cobalt-60 Gamma-Ray Radiation Testing

In this paper, a comparison between the effects of irradiating microelectronics with high energy electrons and Cobalt-60 gamma-rays is examined. Additionally, the effect of electron energy is also discussed. A variety of part types are investigated, including discrete bipolar transistors, hybrids, and junction field effect transistors

Boutte, Alvin J.↗

ASIC/FPGA Trust Assessment Framework

NASA Electronic Parts and Packaging (NEPP) is developing a process to be employed in critical applications. The framework assesses levels of Trust and assurance in microelectronic systems. The process is being created with participation from a variety of organizations. We present a synopsis of the framework that includes contributions from The Aerospace Corporation.

Application specific integrated circuit (ASIC)↗

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

microchannel↗

Single-Event Latchup Measurements on COTS Electronic Devices for Use in ISS Payloads

This paper reports recent single-event latchup results for a variety of microelectronic devices that include an ADC, OpAmp, EEPROM, CPLD, PWM, transceiver, voltage regulator, digital signal processor, step-down converter, buck controller and supervisory circuits. The data were collected to evaluate these devices for possible use in NASA ISS payloads.

Irom, Farokh↗

NASA 2009 Body of Knowledge (BoK) carbon nanotube technology

The nature of the bonding of a nanotube is described by applied quantum chemistry, specifically, orbital hybridization. The chemical bonding of nanotubes is composed entirely of sp2 bonds, similar to those of graphite. This bonding structure, which is stronger than the sp3 bonds found in diamonds, provides the molecules with their unique strength. Nanotubes naturally align themselves into "ropes" held together by Van der Waals forces. Under high pressure, nanotubes can merge together, trading some sp² bonds for sp³ bonds, giving the possibility of producing strong, unlimited-length wires through high-pressure nanotube linking. This document looks at the topic of carbon nanotubes as it applies to microelectronics packaging and assembly.

Gerke, David↗

Recent photonics activites under the NASA electronic parts and packaging (NEPP) program

With the rapidly increasing insertion of photonic devices, circuits and subsystems into NASA spacecraft, a variety of issues associated with reliability and radiation tolerance have arisen. In this paper, we discuss these issues from the perspective of the work currently ongoing in the NASA Electronic Parts and Packaging (NEPP) Program. This Program is focused on evaluating the reliability and radiation response of advanced and emerging microelectronics and photonics technologies of interest to NASA spacecraft system designers.

NEEP↗

TERA-OPS Processing for ATR

A three-dimensional microelectronic device (3DANN-R) capable of performing general image convolution at the speed of 10***sup12*** operations/second (ops) in a volume of less than 1.5 cubic centimeter has been successfully built under the BMDO/JPL VIGILANTE program.

Automatic↗

NASA'S 3D FLIGHT COMPUTER FOR SPACE APPLICATIONS

The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998.

New↗

A History of GPS Sounding

The roots of GPS sounding go back to the first days of interplanetary flight. Today we have the almost concurrent emergence of the very element vital to a new global enterprise in GPS sounding: copious high beacons at ideal frequencies bathing the globe; a profusion of low obiters carrying GPS receivers and designed for real-time global data transfer; low-cost microelectronics of unprecedented power; and the occultation techniques itself the most precise and arguably the simplest atmospheric probe yet devised.

occultation↗

Deep Space One: NASA's First Deep-Space Technology Validation Mission

Under development for launch in July 1998, Deep Space One (DS1) is the first flight of NASA's New Millennium Program, Chartered to validate selected technologies required for future low-cost space science programs. Advanced technologies chosen for validation on DS1 include solar electric propulsion, high-power solar concentrator arrays, autonomous on-board optical navigation, two low-mass science instrument packages, and several telecommunications and microelectronics devices.

Deep↗

Algorithms for High-Speed Universal Noiseless Coding

This paper provides the basic algorithmic definitions and performance characterizations for a high-performance adaptive noiseless coding module which is currently under separate development as single-chip microelectronic circuits at two NASA centers.

Algorithms↗

Pluto Express: Advanced Technologies Enable Lower Cost Missions to the Outer Solar System and Beyond

Missions to Pluto and the outer Solar System are typically driven by factors which tend to increase cost, such as: long life, high radiation exposure, a large power source, high (delta)V requirements, difficult telecommunications links, low solar illumination at the destination, and demanding science measurements. Advanced technology is a central part of responding to such challenges in a manner which permits the cost of development and operations to be an order of magnitude less than for prior outer planet missions...This paper summarizes the curent technology development plan which is tightly coupled to the New Millenium Program (NMP) Deep Space 1 technology validation flight. Specific details will be presented about advanced microelectronics technology.

New↗

One NASA PEM qualification standard : comparison of JPL and GSFC standards

Although use of Plastic Encapsulated Microelectronics (PEMs) in space applications is discouraged, their use is mandatory for selected applications involving the need for advanced technology and small packages. Various space systems designers and manufacturers have developed methods to qualify and screen PEMs. In general, each procedure is different. The purpose of this fiscal year’s investigation is to initiate a process to coordinate the efforts at various NASA centers to eventually develop a One NASA method. Part of this activity includes sharing of test data and PEM qualification methodologies. Various experts in the NASA community were identified and contacted to support this effort. We were successful in finding such experts at GSFC, APL and the Constellation office (Orion and Ares). All these experts provided typical qualification program plans. Since funding was severely restricted, it was decided to concentrate on coordination activity with GSFC. GSFC is planning a new version of IEEE-INST-002 section applying to PEMs. The GSFC expert (Dr. Alexander Teverovsky) provided a detailed assessment of the differences between the planned new version of IEEE-INST-002 and the JPL-D-19426 (JPL guideline) as well as a summary rationale for the decisions within the IEEE-INST-002. It should be noted that GSFC’s assessment of IEEE-INST-002 in the area of PEMs is not finalized. JPL is also considering changes in PEM qualification methodologies based on test data from recent qualification testing for their newer Projects (MSL, Grail, Juno). A spreadsheet delineating the differences between the JPL standard and the GSFC standard is presented.

Cooper, Mark↗

3D X-ray CT for BGA/CGA Workmanship Defect Detection

Commercial-off-the-shelf (COTS) advanced microelectronic technologies in high-reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. One of the key drawbacks of advanced electronic packages with hidden solder joint interconnections, such as the column grid array (CGA), is that inspection can be challenging—whether visually or using X-rays. In general, inspection for solder joint integrity is poor, except for identifying shorts. The new, advanced X-ray systems, especially the 3D computer tomography version, may be able to provide the three-dimensional features that are extremely difficult to resolve under the 2D systems.This report presents both 2D and 3D X-ray images along with their representative optical photomicrographs for a number of advanced electronics package assemblies including 3D stack and CGA assemblies before and after thermal cycling.

Ghaffarian, Reza↗

NESC Assessment – Recommendations on Use of Commercial-Off-The-Shelf (COTS) Parts for NASA Missions

This is to present the NESC assessment "Recommendations on Use of Commercial-Off-The-Shelf (COTS) Electrical, Electronic, and Electromechanical (EEE) Parts for NASA Missions" at the Microelectronics Reliability and Qualification Workshop hosted by Aerospace Corporation in February 8-10, 2022. The assessment has two Phases, Phase I on NASA Center current practices on use of COTS and Phase II on DoD and FAA current practices on use of COTS and NESC guidance on COTS selection, application and verification processes. Phase I report was published as NASA/TM−20205011579 and NESC-RP-19-01490 in December 2020. The presentation also includes the scope of the Phase II of the assessment, which is expected to be completed in March-April, 2022.

EEE parts↗