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At least 973 records · Page 54

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NASA NTRS1990

Optimal block cosine transform image coding for noisy channels

The two dimensional block transform coding scheme based on the discrete cosine transform was studied extensively for image coding applications. While this scheme has proven to be efficient in the absence of channel errors, its performance degrades rapidly over noisy channels. A method is presented for the joint source channel coding optimiaation of a scheme based on the 2-D block cosine transorm when the output of the encoder is to be transmitted via a memoryless design of the quantizers used for encoding the transform coefficients. This algorithm produces a set of locally optimum quantizers and the corresponding binary code assignment for the assumed transform coefficient statistics. To determine the optimum bit assignment among the transform coefficients, an algorithm was used based on the steepest descent method, which under certain convexity conditions on the performance of the channel optimized quantizers, yields the optimal bit allocation. Comprehensive simulation results for the performance of this locally optimum system over noise channels were obtained and appropriate comparisons against a reference system designed for no channel error were rendered.

Vaishampayan, Vinay A.↗

NASA NTRS1989

Psychophysical rating of image compression techniques

Image compression schemes abound with little work which compares their bit-rate performance based on subjective fidelity measures. Statistical measures of image fidelity, such as squared error measures, do not necessarily correspond to subjective measures of image fidelity. Most previous comparisons of compression techniques have been based on these statistical measures. A psychophysical method has been used to estimate, for a number of compression techniques, a threshold bit-rate yielding a criterion level of performance in discriminating original and compressed images. The compression techniques studied include block truncation, Laplacian pyramid, block discrete cosine transform, with and without a human visual system scaling, and cortex transform coders.

Stein, Charles S.↗

NASA NTRS1989

Read disturb errors in a CMOS static RAM chip

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

Wood, Steven H.↗

NASA NTRS1991

Interface Circuit For Printer Port

Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

Tucker, Jerry H.↗

NASA NTRS1991

Modular VLSI Reed-Solomon Decoder

Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

Hsu, In-Shek↗

NASA NTRS1991

Magnet/Hall-Effect Random-Access Memory

In proposed magnet/Hall-effect random-access memory (MHRAM), bits of data stored magnetically in Perm-alloy (or equivalent)-film memory elements and read out by using Hall-effect sensors to detect magnetization. Value of each bit represented by polarity of magnetization. Retains data for indefinite time or until data rewritten. Speed of Hall-effect sensors in MHRAM results in readout times of about 100 nanoseconds. Other characteristics include high immunity to ionizing radiation and storage densities of order 10(Sup6)bits/cm(Sup 2) or more.

Wu, Jiin-Chuan↗

NASA NTRS1990

The impact of NRZ data asymmetry on the performance of a space telemetry system

The telemetry data asymmetry due to rising and falling voltage transitions can cause undesired spectral components at the output of a spacecraft transmitter. The performance of a space telemetry system can potentially degrade because of these undesired components. Here, an expression is derived for the power spectral density of an asymmetric nonreturn-to-zero (NRZ) data stream. This formula is then used to investigate how the data bandwidth varies with data asymmetry. At the receiver end, the threshold levels of undesired spectral components that fall into the carrier-tracking-loop bandwidth are determined by examining the derived spectral density. Further, based on this formula, a simple technique is developed for the computation of bit signal-to-noise ratio (SNR) degradation due to data asymmetry. The telemetry bit SNR degradations derived using this technique are compared with results obtained previously and with measurements by the Electronic Systems Test Laboratory (ESTL) at the Lyndon B. Johnson Space Center.

Nguyen, T. M.↗

NASA NTRS1990

On complexity of trellis structure of linear block codes

The trellis structure of linear block codes (LBCs) is discussed. The state and branch complexities of a trellis diagram (TD) for a LBC is investigated. The TD with the minimum number of states is said to be minimal. The branch complexity of a minimal TD for a LBC is expressed in terms of the dimensions of specific subcodes of the given code. Then upper and lower bounds are derived on the number of states of a minimal TD for a LBC, and it is shown that a cyclic (or shortened cyclic) code is the worst in terms of the state complexity among the LBCs of the same length and dimension. Furthermore, it is shown that the structural complexity of a minimal TD for a LBC depends on the order of its bit positions. This fact suggests that an appropriate permutation of the bit positions of a code may result in an equivalent code with a much simpler minimal TD. Boolean polynomial representation of codewords of a LBC is also considered. This representation helps in study of the trellis structure of the code. Boolean polynomial representation of a code is applied to construct its minimal TD. Particularly, the construction of minimal trellises for Reed-Muller codes and the extended and permuted binary primitive BCH codes which contain Reed-Muller as subcodes is emphasized. Finally, the structural complexity of minimal trellises for the extended and permuted, and double-error-correcting BCH codes is analyzed and presented. It is shown that these codes have relatively simple trellis structure and hence can be decoded with the Viterbi decoding algorithm.

Lin, Shu↗

NASA NTRS1990

Efficient detection and signal parameter estimation with application to high dynamic GPS receiver

In a system for deriving position, velocity, and acceleration information from a received signal emitted from an object to be tracked wherein the signal comprises a carrier signal phase modulated by unknown binary data and experiencing very high Doppler and Doppler rate, this invention provides combined estimation/detection apparatus for simultaneously detecting data bits and obtaining estimates of signal parameters such as carrier phase and frequency related to receiver dynamics in a sequential manner. There is a first stage for obtaining estimates of the signal parameters related to phase and frequency in the vicinity of possible data transitions on the basis of measurements obtained within a current data bit. A second stage uses the estimates from the first stage to decide whether or not a data transition has actually occurred. There is a third stage for removing data modulation from the received signal when a data transition has occurred and a fourth stage for using the received signal with data modulation removed therefrom to update global parameters which are dependent only upon receiver dynamics and independent of data modulation. Finally, there is a fifth stage for using the global parameters to determine the position, velocity, and acceleration of the object.

Kumar, Rajendra↗

NASA NTRS1990

VIPER project

The VIPER project has so far produced a formal specification of a 32 bit RISC microprocessor, an implementation of that chip in radiation-hard SOS technology, a partial proof of correctness of the implementation which is still being extended, and a large body of supporting software. The time has now come to consider what has been achieved and what directions should be pursued in the future. The most obvious lesson from the VIPER project was the time and effort needed to use formal methods properly. Most of the problems arose in the interfaces between different formalisms, e.g., between the (informal) English description and the HOL spec, between the block-level spec in HOL and the equivalent in ELLA needed by the low-level CAD tools. These interfaces need to be made rigorous or (better) eliminated. VIPER 1A (the latest chip) is designed to operate in pairs, to give protection against breakdowns in service as well as design faults. We have come to regard redundancy and formal design methods as complementary, the one to guard against normal component failures and the other to provide insurance against the risk of the common-cause failures which bedevil reliability predictions. Any future VIPER chips will certainly need improved performance to keep up with increasingly demanding applications. We have a prototype design (not yet specified formally) which includes 32 and 64 bit multiply, instruction pre-fetch, more efficient interface timing, and a new instruction to allow a quick response to peripheral requests. Work is under way to specify this device in MIRANDA, and then to refine the spec into a block-level design by top-down transformations. When the refinement is complete, a relatively simple proof checker should be able to demonstrate its correctness. This paper is presented in viewgraph form.

Kershaw, John↗

NASA NTRS1991

Error control techniques for satellite and space communications

Shannon's capacity bound shows that coding can achieve large reductions in the required signal to noise ratio per information bit (E sub b/N sub 0 where E sub b is the energy per bit and (N sub 0)/2 is the double sided noise density) in comparison to uncoded schemes. For bandwidth efficiencies of 2 bit/sym or greater, these improvements were obtained through the use of Trellis Coded Modulation and Block Coded Modulation. A method of obtaining these high efficiencies using multidimensional Multiple Phase Shift Keying (MPSK) and Quadrature Amplitude Modulation (QAM) signal sets with trellis coding is described. These schemes have advantages in decoding speed, phase transparency, and coding gain in comparison to other trellis coding schemes. Finally, a general parity check equation for rotationally invariant trellis codes is introduced from which non-linear codes for two dimensional MPSK and QAM signal sets are found. These codes are fully transparent to all rotations of the signal set.

Costello, Daniel J., Jr.↗

NASA NTRS1991

Biological neural networks as model systems for designing future parallel processing computers

One of the more interesting debates of the present day centers on whether human intelligence can be simulated by computer. The author works under the premise that neurons individually are not smart at all. Rather, they are physical units which are impinged upon continuously by other matter that influences the direction of voltage shifts across the units membranes. It is only the action of a great many neurons, billions in the case of the human nervous system, that intelligent behavior emerges. What is required to understand even the simplest neural system is painstaking analysis, bit by bit, of the architecture and the physiological functioning of its various parts. The biological neural network studied, the vestibular utricular and saccular maculas of the inner ear, are among the most simple of the mammalian neural networks to understand and model. While there is still a long way to go to understand even this most simple neural network in sufficient detail for extrapolation to computers and robots, a start was made. Moreover, the insights obtained and the technologies developed help advance the understanding of the more complex neural networks that underlie human intelligence.

Ross, Muriel D.↗

NASA NTRS1990

Ground states of partially connected binary neural networks

Neural networks defined by outer products of vectors over (-1, 0, 1) are considered. Patterns over (-1, 0, 1) define by their outer products partially connected neural networks consisting of internally strongly connected, externally weakly connected subnetworks. Subpatterns over (-1, 1) define subnetworks, and their combinations that agree in the common bits define permissible words. It is shown that the permissible words are locally stable states of the network, provided that each of the subnetworks stores mutually orthogonal subwords, or, at most, two subwords. It is also shown that when each of the subnetworks stores two mutually orthogonal binary subwords at most, the permissible words, defined as the combinations of the subwords (one corresponding to each subnetwork), that agree in their common bits are the unique ground states of the associated energy function.

Baram, Yoram↗

NASA NTRS1990

Response of a DRAM to single-ion tracks of different heavy-ion species and stopping powers

Multiple-bit errors caused by single-ion tracks in a 256-kb DRAM fabricated by a bulk process were observed for different ion species and stopping power values. The results demonstrate the utility of this device for the evaluation of ion-beam uniformity and ion-beam-induced charge collection in IC devices. The data indicate that single-ion-induced charge transport results in multiple-bit error clusters due to lateral diffusion of excess minority carriers (electrons). Charge collection occurred from a depth of up to 35 microns from the surface of the device. An apparent charge loss was observed for very heavy ions with a high stopping power (Au at 350 MeV).

Zoutendyk, J. A.↗

NASA NTRS1990

RF/optical interference design for optical intersatellite links

A design approach for the RF/optical link interface for a data relay satellite is described. The flexibility of forward and return links in future data acquisition satellites in handling varying missions and data rates to 1 Gbit/s is considered. Attention is focused on requirements for the NASA Tracking and Data Acquisition System. System components are described including the return link multiplexer, the return link transmultiplexer, the forward link multiplexer, the forward link demultiplexer, and the frontside/backside switch. Ping-pong buffers, which provide rate buffering for each input data stream, are discussed and justification bits, which handle variations due to Doppler shift and local oscillator variation, are considered. The time-division multiplexed streams consist of a unique synchronization word for frame synchronization, and control words associated with each data burst to identify the presence or absence of a justification bit. Redundant data paths are described for both forward and return data streams.

Garlow, Ronald K.↗

NASA NTRS1991

An area model for on-chip memories and its application

An area model suitable for comparing data buffers of different organizations and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage. The model gave less than 10 percent error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches, direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas, both direct-mapped and set-associative caches perform better than fully associative caches.

Mulder, Johannes M.↗

NASA NTRS1991

A design approach for ultrareliable real-time systems

A design approach developed over the past few years to formalize redundancy management and validation is described. Redundant elements are partitioned into individual fault-containment regions (FCRs). An FCR is a collection of components that operates correctly regardless of any arbitrary logical or electrical fault outside the region. Conversely, a fault in an FCR cannot cause hardware outside the region to fail. The outputs of all channels are required to agree bit-for-bit under no-fault conditions (exact bitwise consensus). Synchronization, input agreement, and input validity conditions are discussed. The Advanced Information Processing System (AIPS), which is a fault-tolerant distributed architecture based on this approach, is described. A brief overview of recent applications of these systems and current research is presented.

Lala, Jaynarayan H.↗

NASA NTRS1991

Nonuniform visual pattern image sequence coding

Visual Pattern Image Sequence Coding (VPISC) is a pyramidal image coding scheme which utilizes human visual system (HVS) properties to achieve low bit rates while maintaining a good perceived image quality, all with extremely low computational cost. This paper describes extensions of VPISC, termed Foveal VPISC (FVPISC) and Adaptive VPISC (AVPISC). Both algorithms produce decreased bit rates by selectively allowing some image regions to be coded at low resolution. In FVPISC, a foveation criterion is used to select a region of interest. In AVPISC, the algorithm adaptively determines which regions require high-resolution coding in order to maintain uniform image quality over the entire image.

Silsbee, Peter L.↗