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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A three-dimensional microelectronic device (3DANN-R) capable of performing general image convolution at the speed of 10***sup12*** operations/second (ops) in a volume of less than 1.5 cubic centimeter has been successfully built under the BMDO/JPL VIGILANTE program.
The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998.
The roots of GPS sounding go back to the first days of interplanetary flight. Today we have the almost concurrent emergence of the very element vital to a new global enterprise in GPS sounding: copious high beacons at ideal frequencies bathing the globe; a profusion of low obiters carrying GPS receivers and designed for real-time global data transfer; low-cost microelectronics of unprecedented power; and the occultation techniques itself the most precise and arguably the simplest atmospheric probe yet devised.
Under development for launch in July 1998, Deep Space One (DS1) is the first flight of NASA's New Millennium Program, Chartered to validate selected technologies required for future low-cost space science programs. Advanced technologies chosen for validation on DS1 include solar electric propulsion, high-power solar concentrator arrays, autonomous on-board optical navigation, two low-mass science instrument packages, and several telecommunications and microelectronics devices.
This paper provides the basic algorithmic definitions and performance characterizations for a high-performance adaptive noiseless coding module which is currently under separate development as single-chip microelectronic circuits at two NASA centers.
Missions to Pluto and the outer Solar System are typically driven by factors which tend to increase cost, such as: long life, high radiation exposure, a large power source, high (delta)V requirements, difficult telecommunications links, low solar illumination at the destination, and demanding science measurements. Advanced technology is a central part of responding to such challenges in a manner which permits the cost of development and operations to be an order of magnitude less than for prior outer planet missions...This paper summarizes the curent technology development plan which is tightly coupled to the New Millenium Program (NMP) Deep Space 1 technology validation flight. Specific details will be presented about advanced microelectronics technology.
Although use of Plastic Encapsulated Microelectronics (PEMs) in space applications is discouraged, their use is mandatory for selected applications involving the need for advanced technology and small packages. Various space systems designers and manufacturers have developed methods to qualify and screen PEMs. In general, each procedure is different. The purpose of this fiscal year’s investigation is to initiate a process to coordinate the efforts at various NASA centers to eventually develop a One NASA method. Part of this activity includes sharing of test data and PEM qualification methodologies. Various experts in the NASA community were identified and contacted to support this effort. We were successful in finding such experts at GSFC, APL and the Constellation office (Orion and Ares). All these experts provided typical qualification program plans. Since funding was severely restricted, it was decided to concentrate on coordination activity with GSFC. GSFC is planning a new version of IEEE-INST-002 section applying to PEMs. The GSFC expert (Dr. Alexander Teverovsky) provided a detailed assessment of the differences between the planned new version of IEEE-INST-002 and the JPL-D-19426 (JPL guideline) as well as a summary rationale for the decisions within the IEEE-INST-002. It should be noted that GSFC’s assessment of IEEE-INST-002 in the area of PEMs is not finalized. JPL is also considering changes in PEM qualification methodologies based on test data from recent qualification testing for their newer Projects (MSL, Grail, Juno). A spreadsheet delineating the differences between the JPL standard and the GSFC standard is presented.
Commercial-off-the-shelf (COTS) advanced microelectronic technologies in high-reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. One of the key drawbacks of advanced electronic packages with hidden solder joint interconnections, such as the column grid array (CGA), is that inspection can be challenging—whether visually or using X-rays. In general, inspection for solder joint integrity is poor, except for identifying shorts. The new, advanced X-ray systems, especially the 3D computer tomography version, may be able to provide the three-dimensional features that are extremely difficult to resolve under the 2D systems.This report presents both 2D and 3D X-ray images along with their representative optical photomicrographs for a number of advanced electronics package assemblies including 3D stack and CGA assemblies before and after thermal cycling.
This paper reports recent single-event latchup results for a variety of microelectronic devices that include Wireless and Powerline Network Communication devices. The data were collected to evaluate these devices for possible use in NASA Mars missions.
This is to present the NESC assessment "Recommendations on Use of Commercial-Off-The-Shelf (COTS) Electrical, Electronic, and Electromechanical (EEE) Parts for NASA Missions" at the Microelectronics Reliability and Qualification Workshop hosted by Aerospace Corporation in February 8-10, 2022. The assessment has two Phases, Phase I on NASA Center current practices on use of COTS and Phase II on DoD and FAA current practices on use of COTS and NESC guidance on COTS selection, application and verification processes. Phase I report was published as NASA/TM−20205011579 and NESC-RP-19-01490 in December 2020. The presentation also includes the scope of the Phase II of the assessment, which is expected to be completed in March-April, 2022.
The Nowcast of Aerospace Ionizing RAdiation System (NAIRAS) model is a real-time, global, physics-based model originally developed to predict exposure from cosmic radiation to air travelers from both galactic and solar sources. A prototype operational NAIRAS model has provided tabular and graphical data products via its public web site for about ten years. A new version of the NAIRAS model has been developed that incorporates an extension of the model domain from the atmospheric ionizing radiation environment to the space radiation environment, with the addition of the trapped inner belt proton source and altitude-dependent and rigidity-dependent geomagnetic shielding of the galactic cosmic rays (GCR) and solar energetic particle (SEP) protons. New output products of differential and integral particle flux have been developed for the characterization of single-event effects (SEE), expanding the application of NAIRAS from human radiation exposure assessment to allowing end-users to quantify radiation environment risks to aviation and spacecraft microelectronic systems. The NAIRAS model has transitioned to prototype operations at the Community Coordinated Modeling Center (CCMC) where the model now operates in two modes: (1) real-time global predictions of the atmospheric radiation environment and (2) a run-on-request (RoR) service allowing the user to select a specific time period for the global dosimetric calculations, or to upload an aircraft, balloon, or spaceflight trajectory file to provide predictions of the dosimetric and particle flux quantities along the flight path. The new features of NAIRAS version 3.0 are described in this paper and example results of the new output products for low-Earth orbit (LEO), medium-Earth orbit (MEO), and free-space radiation environments are presented
The HOTS program will develop a technology for high-bandwidth, high-dynamic-range sensing at high temperature. Performance will be validated through the development and demonstration of a pressure sensor module (i.e., integrated transducer and signal-conditioning microelectronics) achieving the following performance goals: NASA Glenn has unique technology experience in extreme environment pressure sensors & IC electronics, including at 800 °C in air, providing significant risk reduction in meeting DARPA HOTS goals. Appropriate partnership and tech transfer should accelerate realization of DARPA HOTS hard technical challenges.
A probabilistic total ionizing dose (TID) failure assessment is extended to include survivor data, enabling the bounding of failure probability to a desired confidence level (CL) without failure data. The extension provides an avenue for analyzing microelectronics tested for TID without reaching a failure mode, a scenario often encountered by missions utilizing commercial-off-the-shelf (COTS) technologies. Using the type-I censored likelihood formulation and a realistic upper bound on expected device performance, the failure probability space is bounded by confidence contours within the context of a variable environment. The framework accommodates any type of distribution assumed for the part failure or the environment under consideration. Furthermore, the framework can be utilized pre-emptively to plan future device TID tests, minimizing costs while meeting survival requirements. Heritage data may also be used as survivors to further minimize testing costs when parts are from the same lot, but the amount of constraint derived from heritage is limited. Altogether, the framework enables a formal, mathematically rigorous analysis of radiation tolerant devices tested to a maximum dose, as well as flight heritage, in a hardness assurance methodology.
The rapid evolution of electronics has heralded countless benefits to humanity, enabling increases in computing power while decreasing costs. However, the constantly changing semiconductor device landscape proves to be an immense challenge for the reliability community, especially for those concerned with radiation effects on microelectronics. Changes in device manufacturing, from device structure to processing steps, may and often do change the way the device responds to radiation. While radiation hardened parts are not as much of a reliability concern, they also lag behind commercial off-the-shelf, or COTS, parts in terms of computing capabilities, some by over a decade. Many missions may have no choice but to utilize COTS. As such, these missions need to ensure their parts are reliable in the face of total ionizing dose (TID). However, part and testing facility costs limit the amount of testing possible.
This report provides a parts list, with assembly and programming instructions for building firstgeneration (Mark I) compact test ovens; this oven design is customized for prolonged functional electrical testing of prototype silicon carbide (SiC) devices at temperatures up to 500 °C (932 °F). The general approach of using multiple compact ovens to perform long-term, high-temperature electronics testing efficiently is described in a conference paper (Izadnegahdar, Alain, et al.: Alternative Setup for LongDuration Low-Duty-Cycle 600 °C Ambient Testing of SiC Integrated Circuits. International Microelectronics Assembly and Packaging Society (iMAPS) HiTECH 2021 Technology Crossover Extravaganza, 2021), available at https://ntrs.nasa.gov/citations/20210011676. The new Mark I oven design described here offers several significant improvements over the compact oven described in that paper. For example, it is constructed from commercial off-the-shelf (COTS) components and requires minimal assembly. Much of the work involves drilling holes in the two aluminum project boxes, which contain the control electronics and the oven itself. The cost of components is less than $200 (USD) per oven, which makes constructing multiple ovens affordable. In addition, the two-box design separates the high-temperature heater from the electronics, which keeps the electronics cool, prolonging the lifetime of these components.
SEL is a serious obstacle to use of state-of-the-art microelectronics, and a priori prediction of SEL susceptibility has proven elusive. We develop SEL risk-assessment tools based on analysis of large archives of SEL test data for unhardened CMOS parts. Results include a flexible method for bounding SEL rates even with minimal test data.
Next generation gas turbine engine health monitoring for high performance jet engine-powered aircraft will incorporate integrated microelectronic sensors specifically designed to enhance aircraft functionality, engine efficiency, and safety. Temperature, air flow and pressure associated with the gas path as well as emissions from the engine correlate to the state of the combustor and other engine health conditions. Monitoring these parameters accurately requires positioning electronic sensors in the hot zone of the gas turbine engine, which exposes them to temperatures in excess of 400ºC. At these temperatures, signal amplification is needed at the transducer level to distinguish the desired measured signal from the significant electronic noise generated by the harsh environment. In this presentation, we report on the simulation, development, fabrication, and testing on a high temperature Class-A amplifier which utilizes a 4H-SiC Static Induction Transistor (SIT) as the active device and input/output matching and DC bias networks comprised of thin-film spiral inductors, metal-insulator-metal capacitors, and thick film chip resistors. A small signal model that emulates the operation of the 4H-SiC SIT from 25 to 400ºC, with an emphasis on operation at 400οC, was utilized. Measurements were performed from 25 to 400ºC to generate current-voltage curves, capacitive transistor characteristics and high frequency scattering parameters (S-parameters). The measured data was used to extrapolate the transconductance, gm, as a function of temperature for model development. Circuit simulation tools were used to generate S-parameters, which were compared to the measured values. At 400οC, a maximum difference between measured and simulated S-parameters for frequencies from 20 to 100 MHz were 3.84%, 0.68%, 10.61%, and 3.26% for S21, S12, S11, and S22, respectively. The average transit frequency, ft, was calculated from measured values to be 197.8 MHz, while the simulated value from the model was found to be 200 MHz. The Amplifier’s S-parameters were recorded at 20-100 MHz over a temperature range of 25-400ºC and show a gain of approximately 15.8 and 5.80 dBm at 25 and 400ºC, respectively. The input and output reflection coefficients at 50 MHz and 400ºC were -18.5 and -15.2 dB, respectively. The noise figure and phase noise were measured over the temperature range of 25-400ºC and recorded. The noise figure increased 21% at 50 MHz over the temperature range, while the 1 kHz offset of the phase noise remained below -110 dB. The stability factor, K, calculated with measured and simulated data demonstrates unconditional stability over the frequency range at 400ºC. Lastly, the 1-dB compression point was measured at 50 MHz and 400ºC with an approximated output of 9.5 dBm.
Thicker electrodes are provided on microelectronic device using thermo-compression bonding. A thin-film electrical conducting layer forms electrical conduits and bulk depositing provides an electrode layer on the thin-film electrical conducting layer. An insulating polymer layer encapsulates the electrically thin-film electrical conducting layer and the electrode layer. Some of the insulating layer is removed to expose the electrode layer.