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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 973 records · Page 54
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗
DOE OSTI2020

Large-Scale Adoption of Self-Synchronized Universal Droop Controller-Based Inverters to Enable Ancillary Services for Different Modes of Distribution System Operations

This work proposes the large-scale adoption of self-synchronized universal droop controller (SUDC)-based inverters to enable ancillary services for different modes of distribution system operations. The IEEE 123 bus system was modeled on a real-time simulator to study the performance of large-scale adoption of SUDC inverters in a distribution system. The resulting data collected shows that the voltage and the frequency were regulated within ranges, such as less than 5% for voltage and less than 0.5% for frequency, under different load variations and grid operations. Also, the black start was achieved within 0.4 s without any voltage overshoot. Through the simulation and validation on a small microgrid and the IEEE 123 bus distribution system, it can be concluded that the SUDC was successfully adopted to regulate the voltage and the frequency within the given ranges, and black start achieved within 1 s without voltage overshoot for different modes of distribution system operations.

14 SOLAR ENERGY↗
DOE OSTI2020

Virtual synchronous generator system and method with virtual inertia control

A virtual synchronous generator device disclosed. The device includes an inverter and inverter controller having a power control portion, a power reserve portion, a power point tracking control portion, and a virtual inertia control portion. The power reserve portion determines an amount of power to be reserved and sends a signal, indicative of the determined amount of power to the power point tracking controller. The power point tracking controller determines a power point that is less than a MPP, and provides a signal to the power control portion indicative of the determined power point. The inertia control portion determines a virtual inertia and provides a signal indicative of the virtual inertia to the power control portion. The power control portion provides a power control signal to the inverter based on the power point tracking signal and the inertia command signal.

42 ENGINEERING↗
DOE OSTI2021

Three-phase, three-level inverters and methods for performing soft switching with phase synchronization

A three-phase, N-level inverter and method are disclosed. A circuit topology of the inverter comprises first, second and third sets of switches and first, second and third inductors. Each switch comprises at least first, second and third terminals, the first terminals being control terminals. The first terminals of the first, second and third inductors are electrically coupled to the first, second and third sets of switches, respectively. A current controller performs a control algorithm that causes it to output first, second and third sets of gating signals to the control terminals of the switches of the first, second and third sets of switches, respectively, to cause them to be placed in an on state or an off state in a particular sequence to perform zero voltage switching while maintaining synchronization of the three phases of the three-phase, N-level inverter.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2021

Path-synchronous performance monitoring of interconnection networks based on source code attribution

Examples disclosed herein relate to path-synchronous performance monitoring of an interconnection network based on source code attribution. A processing node in the interconnection network has a profiler module to select a network transaction to be monitored, determine a source code attribution associated with the network transaction to be monitored, and issue a network command to execute the network transaction to be monitored. A logger module creates, in a buffer, a node temporal log associated with the network transaction and the network command. A drainer module periodically captures the node temporal log. The processing node has a network interface controller to receive the network command and mark a packet generated for the network command to be temporally tracked and attributed back to the source code attribution at each hop of the interconnection network traversed by the marked packet.

Chabbi, Milind M.↗
DOE OSTI2021

Synchronization between processes in a coordination namespace

A system and method of supporting point-to-point synchronization among processes/nodes implementing different hardware barriers in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing data, communications, and coordination within applications and workflows implementing barriers in a multi-tier, multi-nodal tree hierarchy. The system provides a hardware accelerated mechanism to support barriers between the participating processes. Also architected is a tree structure for a barrier processing method where processes are mapped to nodes of a tree, e.g., a tree of degree k to provide an efficient way of scaling the number of processes in a tuple space/coordination namespace.

Jacob, Philip↗
DOE OSTI2021

Large-Scale Adoption of Self Synchronized Universal Droop Controller-Based Inverters to Enable Ancillary Services for Different Modes of Distribution System Operations

This poster presents the results of using the self-synchronized universal droop controller to enable solar power to provide ancillary services so that the use of solar power can be increased. A 300-node system using the IEEE 123 bus test feeder are modeled on a real time power system simulator with the results presented.

Arce, Laura↗
DOE OSTI2022

Synchronous High-frequency Distributed Readout For Edge Processing At The Fermilab Main Injector And Recycler

The Main Injector (MI) was commissioned using data acquisition systems developed for the Fermilab Main Ring in the 1980s. New VME-based instrumentation was commissioned in 2006 for beam loss monitors (BLM)[2], which provided a more systematic study of the machine and improved displays of routine operation. However, current projects are demanding more data and at a faster rate from this aging hardware. One such project, Real-time Edge AI for Distributed Systems (READS), requires the high-frequency, low-latency collection of synchronized BLM readings from around the approximately two-mile accelerator complex. Significant work has been done to develop new hardware to monitor the VME backplane and broadcast BLM measurements over Ethernet, while not disrupting the existing operations critical functions of the BLM system. This paper will detail the design, implementation, and testing of this parallel data pathway.

43 PARTICLE ACCELERATORS↗
DOE OSTI2023

Synchronization of Electric Power Networks

Invited contribution to the ITU News Magazine – Special Edition on “Future use and applications of the Coordinated Universal Time (UTC)” a joint ITU-BIPM initiative. The ITU will produce a special edition of its ITU News Magazine that will feature the “Future use and applications of the Coordinated Universal Time (UTC)”, a joint ITU-BIPM initiative, planned for publication in March or April, 2023. The main objective of the magazine is to educate telecommunication society about existing status of UTC applications, objectives, and possible ways to resolve the leap second issues. This article on “Synchronization of electrical distribution networks” for this edition, highlighting some of the key issues that will help the understanding of the important issues that are related to the coordinated universal time (UTC) and its dissemination.

Dagle, Jeffery E.↗
DOE OSTI2022

Synchronized electric meter having an atomic clock

Smart electric meters configured to perform fast, time-synchronized electrical energy measurements at the consumer-level are disclosed herein. In some embodiments, a smart electric meter includes circuitry configured to measure an electrical value at a location of an end user in a power system. The smart electric meter can further include an atomic clock configured to output a timing signal, and a controller configured to receive (a) the measured electrical value from the circuitry and (b) the timing signal from the atomic clock. The controller can further (a) process the electrical value to generate meter data and (b) generate a time tag based on the timing signal. Then, the controller can associate the time tag with the meter data to generate time-tagged meter data.

Min, Liang↗
DOE OSTI2022

Synchronization between processes in a coordination namespace

A system and method of supporting point-to-point synchronization among processes/nodes implementing different hardware barriers in a tuple space/coordinated namespace (CNS) extended memory storage architecture. The system-wide CNS provides an efficient means for storing data, communications, and coordination within applications and workflows implementing barriers in a multi-tier, multi-nodal tree hierarchy. The system provides a hardware accelerated mechanism to support barriers between the participating processes. Also architected is a tree structure for a barrier processing method where processes are mapped to nodes of a tree, e.g., a tree of degree k, to provide an efficient way of scaling the number of processes in a tuple space/coordination namespace.

Jacob, Philip↗
DOE OSTI2023

Sampling synchronization through GPS signals

A method uses a distributed data acquisition system with multiple, physically unconnected, data acquisition units, that can be in wireless communication with a remote host, to timestamp measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. A current absolute time is derived from messages received from a satellite radio beacon positioning system (GPS). Measurement data is sampled by each unit at a specified sampling rate. Using hardware logic, batches of sampled data are associated with corresponding timestamps representing the absolute time at which the data was sampled. Data and timestamps may be transmitted to the host. A time offset bias is compensated by comparing timestamps against a nominal time based on start time and nominal sampling rate. The sampling clock rate may be disciplined using time pulses from the GPS receiver. An initial start of data sampling by all units can also be synchronized.

Zhuge, James Q.↗
DOE OSTI2024

Accelerating Application Bulk Synchronous Writes in HPC Environments

High-bandwidth storage tiers are becoming more common for their capability to absorb high-rate, bursty I/Os. Notably, the designs of these fast storage tiers differ from system to system. The variation of these layers and non-uniform methods of access can pose chal- lenges for applications seeking to run at multiple HPC facilities. Therefore, in this work, we present Spectral, a rapid-output ab- straction library to accelerate application, bulk-synchronous writes on HPC systems. We design Spectral to enable applications to use high-bandwidth storage, such as node-local storage and dis- tributed, write-caches (e.g., burst buffers) transparently without requiring modifications to the application or file system source code. The key idea is to allow applications to spend most of the time performing productive work and to not require any source code changes for maximum portability on different HPC archi- tectures. Spectral internally re-routes write-only files through available, high-performance I/O resources before ultimately mi- grating them to the shared global parallel file system. For instance, on Summit, Spectral transparently places application outputs on node-local storage and then utilizes asynchronous migration to the center-wide GPFS file system. We evaluate Spectral on the Summit HPC system (1024 nodes) using the IOR benchmark and real scientific applications. Spectral shows linear performance scaling, improving application write performance by over an order of magnitude when compared to GPFS.

Khan, Awais↗
DOE OSTI2024

SVM-Based Synchronized Fault Detection for 100% Renewable Microgrids: Preprint

Traditional protection schemes face significant challenges when applied to microgrids with high penetrations of renewables with inverter-based resources (IBRs). The proliferation of advanced sensing and communication technologies has generated copious data, offering an opportunity to overcome these limitations using data-driven machine learning approaches. This work proposes a novel approach based on a support vector machine (SVM) for detecting faults within a 100% renewable microgrid. The approach encompasses a systematic offline training stage for the development of a linear SVM-based fault detection algorithm. This process covers offline data collection from the microgrid under study, the extraction of features such as positive- and negative-sequence components and the total harmonic distortion of the voltage and current measurements of the relays, and the design of the linear SVM-based classifier. During the online implementation, however, different classifiers can exhibit asynchronicity in detecting the fault inception at different subcycle-to-cycle period-level delays. To circumvent this asynchronicity issue, a separate algorithm is developed for each relay to estimate the fault inception time as close to the real fault time. The performance of the proposed SVM-based synchronized fault detection method is evaluated using online time-domain simulation studies on a microgrid test system. The results corroborate the reliability of the fault detection scheme when tested under various fault cases (fault types, locations, and impedances) and non-fault cases during both grid-tied and islanded operation modes.

100% microgrid↗
DOE OSTI2026

Brushless Excitation for Wound-field Synchronous Machines using Multi-harmonic Windings

Wound-field synchronous machines (WFSM) are promising alternatives to electric machines with permanent magnets (PM). The ability to control the rotor field in these machines makes them well-suited to safety critical applications, while the absence of rare-earth permanent magnets makes these machines sustainable. The WFSM rotor excitation schemes have traditionally used carbon brushes, which significantly reduces the reliability of these machines, limiting their widespread adoption. To overcome this limitation and improve the reliability of WFSMs, several brushless rotor excitation schemes have been developed. However, most of these systems require additional windings or dedicated power electronics, making them expensive and limiting achievable power-density. In this paper a new brushless excitation scheme is proposed. In this scheme, a multiphase, multi-harmonic stator winding is designed. This winding can independently control two spatial harmonics in the airgap of the machine; the first to create torque and the second to wirelessly transfer power to the rotor to excite it.

Gadiyar, Nishanth [ORNL] (ORCID:0000000348267524)↗
DOE OSTI2026

Propulsion System Design using a Dual 3-Phase PM Synchronous Reluctance Machine with X-Type Multi-Level GaN Inverter

— A propulsion system design is exhibited here that comprises of an X-type GaN power module based dual multi-level inverter and a PM Synchronous Reluctance motor. With the critical benefits of multi-level operation, namely low common mode EMI noise, low switching loss, low current Total Harmonic Distortion (THD), smoother torque and lower iron loss, this topology targets high system-level efficiency and high power density while using reduced rare earth (RE) elements in its motor. General Motors and Purdue University jointly designed and developed this 800V class, highly scalable traction drive that can deliver 200+ kW of power suitable for C-SUV to truck vehicle class. The 3-phase electric machine design utilizes dual winding with 6 terminals to work in line with the GaN X-type inverter, and results in a tractive solution that ensures higher machine efficiency while reducing cost and uncertainty related to use and availability of heavy rare earth/rare earth elements in its rotor.

MOMEN, FAIZUL [General Motors LLC, Detroit, MI (Un↗