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NASA NTRS1992

ACTS aeronautical experiments

A description of the two aeronautical mobile satellite experiments utilizing NASA's Advanced Communications Technology Satellite (ACTS) is presented. The low bit rate experiment is principally a Ka-band technology demonstration of a prototype 4.8 Kbps aeronautic mobile terminal employing three experimental active electronically steered arrays. The high bit rate experiment can demonstrate a 64 Kbps to 384 Kbps satellite link between a ground terminal and an aircraft.

Nguyen, Tien M.↗

NASA NTRS1991

The effects of long delay and transmission errors on the performance of TP-4 implementations

A set of tools that allows us to measure and examine the effects of transmission delay and errors on the performance of TP-4 implementations has been developed. The tools give insight into both the large- and small-scale behaviors of an implementation. These tools have been systematically applied to a commercial implementation of TP-4. Measurements show, among other things, that a 2-second one-way transmission delay and an effective bit-error rate of 1 error per 100,000 bits can result in a 95 percent reduction in TP-4 throughput. The detailed statistics give insight into why transmission delay and errors affect this implementations so significantly and support a number of 'lessons learned' that could be applied to TP-4 implementations that operate more robustly across networks with long transmission delays and transmission errors.

Durst, Robert C.↗

NASA NTRS1993

Analog-To-Digital Converter For Sum-Of-Squares Measurements

Analog-to-digital converter (ADC) circuit designed as part of larger circuit intended to measure root-mean-square current on 20-kHz powerline. Provides digital output of 11 bits of data plus 1-bit overflow signal at sampling rate of 4 MHz. Output processed by multiplying-and-accumulating circuitry to obtain sum of squares and digitized current samples accumulated during preset number of consecutive sampling periods. Used to digitize current samples from ADC directly as alternative or auxiliary output. Notable features include low power and fast conversion.

Osborn, Stephen H.↗

NASA NTRS1992

Contaminant Interferences with SIMS Analyses of Microparticle Impactor Residues on LDEF Surfaces

Elemental analyses of impactor residues on high purity surface exposed to the low earth orbit (LEO) environment for 5.8 years on Long Duration Exposure Facility (LDEF) has revealed several probable sources for microparticles at this altitude, including natural micrometeorites and manmade debris ranging from paint pigments to bits of stainless steel. A myriad of contamination interferences were identified and their effects on impactor debris identification mitigated during the course of this study. These interferences included pre-, post-, and in-flight deposited particulate surface contaminants, as well as indigenous heterogeneous material contaminants. Non-flight contaminants traced to human origins, including spittle and skin oils, contributed significant levels of alkali-rich carbonaceous interferences. A ubiquitous layer of in-flight deposited silicaceous contamination varied in thickness with location on LDEF and proximity to active electrical fields. In-flight deposited (low velocity) contaminants included urine droplets and bits of metal film from eroded thermal blankets.

Simon, C. G.↗

NASA NTRS1993

Multi-rate, real time image compression for images dominated by point sources

An image compression system recently developed for compression of digital images dominated by point sources is presented. Encoding consists of minimum-mean removal, vector quantization, adaptive threshold truncation, and modified Huffman encoding. Simulations are presented showing that the peaks corresponding to point sources can be transmitted losslessly for low signal-to-noise ratios (SNR) and high point source densities while maintaining a reduced output bit rate. Encoding and decoding hardware has been built and tested which processes 552,960 12-bit pixels per second at compression rates of 10:1 and 4:1. Simulation results are presented for the 10:1 case only.

Huber, A. Kris↗

NASA NTRS1992

Satellite communications application to Pacific countries above Ku band

An application of satellite communications above the Ku band to the Pacific region is described, focusing on: (1) Lightsat system and (2) a high capacity satellite system. A small geostationary satellite system using Ku band for the Federated States of Micronesia is shown as an example. A concept of multi-gigabits/second high capacity communications system using two satellites in the Ka band is described. The onboard bit-by-bit processing is very useful in the low link margin environment due to rain attenuation. These topics were obtained by the Asia Pacific Telecommunications Study granted by NASA conducted by the University of Colorado at Boulder.

Iida, Takashi↗

NASA NTRS1991

Millimeter-wave pseudomorphic HEMT MMIC phased array components for space communications

Recent advances in pseudomorphic HEMT MMIC (PMHEMT/MMIC) technology have made it the preferred candidate for high performance millimeter-wave components for phased array applications. This paper describes the development of PMHEMT/MMIC components at Ka-band and V-band. Specifically, the following PMHEMT/MMIC components will be described: power amplifiers at Ka-band; power amplifiers at V-band; and four-bit phase shifters at V-band. For the Ka-band amplifier, 125 mW output power with 5.5 dB gain and 21 percent power added efficiency at 2 dB compression point has been achieved. For the V-band amplifier, 112 mW output power with 6 dB gain and 26 percent power added efficiency has been achieved. And, for the V-band phase shifter, four-bit (45 deg steps) phase shifters with less than 8 dB insertion loss from 61 GHz to 63 GHz will be described.

Lan, G. L.↗

NASA NTRS1993

Interference effects on Space Station Freedom and space shuttle orbiter Ku-band downlinks

The space shuttle orbiter (SSO) and Ku-band single access return (KSAR) link and the Space Station Freedom (SSF) KSAR link via the tracking and data relay satellite system (TDRSS) use the same carrier frequency. The interference between spacecraft is minimized by opposite antenna polarizations and by TDRSS antenna beam pointing, but if the SSF and SSO are in close proximity, it is expected that mutual interference will be significant. Recently, Tsang and Su (1988, 1989) simulated the mutual interference effects, using a practical nonlinear bandlimited channel. The purpose of this paper is to demonstrate that a simplified (i.e., linear band-limited channel) analytical approach will yield adequate accuracy for the expected range of operating conditions. Relative degradation in bit energy-to-thermal noise power spectral density ratio to achieve a 10 exp -5 coded bit-error-probability is determined to be 4 dB for the Ku-band SSO-to-TDRS I-channel return link with a 4.5 dB effective signal-to-interference total power ratio (S/I) when the Ku-band SSF-to-TDRS return link interferes, whereas Su's simulation yields approximately 5 dB degradation. For the Ku-band SSF-to-TDRS return link, both analysis and simulation results yield a relative signal degradation of 0.4 dB at the effective S/I = 21.6 dB. In conclusion, interference on the Ku-band SSO-to-TDRS I-channel return link is significant, but on the Ku-band SSF-to-TDRS return link it is negligible.

Kwon, Hyuck M.↗

NASA NTRS1992

A VLSI decomposition of the deBruijn graph

The nth order deBruijn graph Bn is the state diagram for an n-stage binary shift register. It is a directed graph with 2 to the n vertices, each labeled with an n-bit binary string, and 2 to the n+1 edges, each labeled with an (n+1)-bit binary string. It is shown that Bn can be built by appropriately connecting together with extra edges many isomorphic copies of a fixed graph, which is called a building block for Bn. The efficiency of such a building block is refined as the fraction of the edges of Bn which are present in the copies of the building block. It is then shown that for any alpha less than 1, there exists a graph which is a building block for Bn of efficiency greater than alpha for all sufficiently large n. The results are illustrated by showing how a special hierarchical family of building blocks has been used to construct a very large Viterbi decoder which will be used on the Galileo mission.

Collins, Oliver↗

NASA NTRS1992

Numerical simulation of a 325 Mbit/s QPPM optical communication system

Optical digital receivers are being considered for intersatellite laser communication links. A demonstration system is being designed to operate at 325 MBit/s, using quaternary pulse position modulation (QPPM). Laboratory experiments have been conducted using a 50 MBit/s prototype system. A numerical model has been developed to simulate a QPPM optical receiver. The 50 MBit/s system was simulated to verify the validity of the model. The model was then used to simulate the projected behavior of the 325 MBit/s system. The model predicts a bit error rate of 10.6 at 38 incident photons per bit for 820 nm light.

Martino, Anthony J.↗

NASA NTRS1992

Real-time processor for staring receivers

The design, fabrication, and testing of a state-of-the-art, high-throughput on-focal plane IR-image signal processor is described. The processing functions performed are frame differencing and thresholding. The final focal plane array will consist of a 128 x 128-pixel platinum-silicide detector bump-mounted to an on-chip CCD multiplexer. The processor is in a 128-channel parallel-pipeline format. Each channel consists of a pixel regenerator (charge differencer), 128-pixel frame store CCD memory, pixel differencer, second pixel regenerator, thresholder (analog comparator), and digital latch. Four parallel analog outputs and four parallel digital outputs are included. The digital outputs provide a bit map of the image. All analog clock signals (128 KHz, 256 KHz, and 5 MHz) are generated by on-chip TTL-input clock drivers. TTL clock driver inputs are generated off-chip. The technology is low-temperature surface and buried channel CCD/CMOS/indium bump. The design goal was 8-bit resolution at 77 K and 1000 frames/s. Applications include point- or extended-target motion detection with thresholding. Design trade-offs and enhancements (such as on-chip detector gain compensation and a simple window processor) are discussed.

Hanzal, Brian↗

NASA NTRS1994

A Motion-Compensating Image-Compression Scheme

Chrominance used (in addition to luminance) in estimating motion. Variable-rate digital coding scheme for compression of color-video-image data designed to deliver pictures of good quality at moderate compressed-data rate of 1 to 2 bits per pixel, or of fair quality at rate less than 1 bit per pixel. Scheme, in principle, implemented by use of commercially available application-specific integrated circuits. Incorporates elements of some prior coding schemes, including motion compensation (MC) and discrete cosine transform (DCT).

Wong, Carol↗

NASA NTRS1993

Image coding using entropy-constrained residual vector quantization

The residual vector quantization (RVQ) structure is exploited to produce a variable length codeword RVQ. Necessary conditions for the optimality of this RVQ are presented, and a new entropy-constrained RVQ (ECRVQ) design algorithm is shown to be very effective in designing RVQ codebooks over a wide range of bit rates and vector sizes. The new EC-RVQ has several important advantages. It can outperform entropy-constrained VQ (ECVQ) in terms of peak signal-to-noise ratio (PSNR), memory, and computation requirements. It can also be used to design high rate codebooks and codebooks with relatively large vector sizes. Experimental results indicate that when the new EC-RVQ is applied to image coding, very high quality is achieved at relatively low bit rates.

Kossentini, Faouzi↗

NASA NTRS1993

Transform coding for space applications

Data compression coding requirements for aerospace applications differ somewhat from the compression requirements for entertainment systems. On the one hand, entertainment applications are bit rate driven with the goal of getting the best quality possible with a given bandwidth. Science applications are quality driven with the goal of getting the lowest bit rate for a given level of reconstruction quality. In the past, the required quality level has been nothing less than perfect allowing only the use of lossless compression methods (if that). With the advent of better, faster, cheaper missions, an opportunity has arisen for lossy data compression methods to find a use in science applications as requirements for perfect quality reconstruction runs into cost constraints. This paper presents a review of the data compression problem from the space application perspective. Transform coding techniques are described and some simple, integer transforms are presented. The application of these transforms to space-based data compression problems is discussed. Integer transforms have an advantage over conventional transforms in computational complexity. Space applications are different from broadcast or entertainment in that it is desirable to have a simple encoder (in space) and tolerate a more complicated decoder (on the ground) rather than vice versa. Energy compaction with new transforms are compared with the Walsh-Hadamard (WHT), Discrete Cosine (DCT), and Integer Cosine (ICT) transforms.

Glover, Daniel↗

NASA NTRS1993

Compact disk error measurements

The objectives of this project are as follows: provide hardware and software that will perform simple, real-time, high resolution (single-byte) measurement of the error burst and good data gap statistics seen by a photoCD player read channel when recorded CD write-once discs of variable quality (i.e., condition) are being read; extend the above system to enable measurement of the hard decision (i.e., 1-bit error flags) and soft decision (i.e., 2-bit error flags) decoding information that is produced/used by the Cross Interleaved - Reed - Solomon - Code (CIRC) block decoder employed in the photoCD player read channel; construct a model that uses data obtained via the systems described above to produce meaningful estimates of output error rates (due to both uncorrected ECC words and misdecoded ECC words) when a CD disc having specific (measured) error statistics is read (completion date to be determined); and check the hypothesis that current adaptive CIRC block decoders are optimized for pressed (DAD/ROM) CD discs. If warranted, do a conceptual design of an adaptive CIRC decoder that is optimized for write-once CD discs.

Howe, D.↗

NASA NTRS1991

Systolic array IC for genetic computation

Measuring similarities between large sequences of genetic information is a formidable task requiring enormous amounts of computer time. Geneticists claim that nearly two months of CRAY-2 time are required to run a single comparison of the known database against the new bases that will be found this year, and more than a CRAY-2 year for next year's genetic discoveries, and so on. The DNA IC, designed at HP-ICBD in cooperation with the California Institute of Technology and the Jet Propulsion Laboratory, is being implemented in order to move the task of genetic comparison onto workstations and personal computers, while vastly improving performance. The chip is a systolic (pumped) array comprised of 16 processors, control logic, and global RAM, totaling 400,000 FETS. At 12 MHz, each chip performs 2.7 billion 16 bit operations per second. Using 35 of these chips in series on one PC board (performing nearly 100 billion operations per second), a sequence of 560 bases can be compared against the eventual total genome of 3 billion bases, in minutes--on a personal computer. While the designed purpose of the DNA chip is for genetic research, other disciplines requiring similarity measurements between strings of 7 bit encoded data could make use of this chip as well. Cryptography and speech recognition are two examples. A mix of full custom design and standard cells, in CMOS34, were used to achieve these goals. Innovative test methods were developed to enhance controllability and observability in the array. This paper describes these techniques as well as the chip's functionality. This chip was designed in the 1989-90 timeframe.

Anderson, D.↗

NASA NTRS1993

Static Computer Memory Integrity Testing (SCMIT): An experiment flown on STS-40 as part of GAS payload G-616

This experiment investigated the integrity of static computer memory (floppy disk media) when exposed to the environment of low earth orbit. The experiment attempted to record soft-event upsets (bit-flips) in static computer memory. Typical conditions that exist in low earth orbit that may cause soft-event upsets include: cosmic rays, low level background radiation, charged fields, static charges, and the earth's magnetic field. Over the years several spacecraft have been affected by soft-event upsets (bit-flips), and these events have caused a loss of data or affected spacecraft guidance and control. This paper describes a commercial spin-off that is being developed from the experiment.

Hancock, Thomas↗

NASA NTRS1993

Radiation hardened microprocessor for small payloads

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

Shah, Ravi↗