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At least 109 records · Page 6

Large-Constraint-Length, Fast Viterbi Decoder

Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

Collins, O.

Truncation effects in Viterbi decoding

Practical Viterbi decoders often fall significantly short of full maximum likelihood decoding performance because of survivor truncation effects. In the present work the authors study the tradeoff between truncation length and performance loss for the two most common variations of Viterbi's algorithm: best-state decoding (BSD) and fixed-state decoding (FSD). It is found that FSD survivors should be about twice as long as BSD survivors for comparable performance.

Mceliece, Robert J.

Modular VLSI Reed-Solomon Decoder

Proposed Reed-Solomon decoder contains multiple very-large-scale integrated (VLSI) circuit chips of same type. Each chip contains sets of logic cells and subcells performing functions from all stages of decoding process. Full decoder assembled by concatenating chips, with selective utilization of cells in particular chips. Cost of development reduced by factor of 5. In addition, decoder programmable in field and switched between 8-bit and 10-bit symbol sizes.

Hsu, In-Shek

Coding gains and error rates from the Big Viterbi Decoder

A prototype hardware Big Viterbi Decoder (BVD) was completed for an experiment with the Galileo Spacecraft. Searches for new convolutional codes, studies of Viterbi decoder hardware designs and architectures, mathematical formulations, and decompositions of the deBruijn graph into identical and hierarchical subgraphs, and very large scale integration (VLSI) chip design are just a few examples of tasks completed for this project. The BVD bit error rates (BER), measured from hardware and software simulations, are plotted as a function of bit signal to noise ratio E sub b/N sub 0 on the additive white Gaussian noise channel. Using the constraint length 15, rate 1/4, experimental convolutional code for the Galileo mission, the BVD gains 1.5 dB over the NASA standard (7,1/2) Maximum Likelihood Convolution Decoder (MCD) at a BER of 0.005. At this BER, the same gain results when the (255,233) NASA standard Reed-Solomon decoder is used, which yields a word error rate of 2.1 x 10(exp -8) and a BER of 1.4 x 10(exp -9). The (15, 1/6) code to be used by the Cometary Rendezvous Asteroid Flyby (CRAF)/Cassini Missions yields 1.7 dB of coding gain. These gains are measured with respect to symbols input to the BVD and increase with decreasing BER. Also, 8-bit input symbol quantization makes the BVD resistant to demodulated signal-level variations which may cause higher bandwidth than the NASA (7,1/2) code, these gains are offset by about 0.1 dB of expected additional receiver losses. Coding gains of several decibels are possible by compressing all spacecraft data.

Onyszchuk, I. M.

Performance of high resolution decoding with Multi-Anode Microchannel Array detectors

The Multi-Anode Microchannel Array (MAMA) is a microchannel plate based photon counting detector with applications in ground-based and space-based astronomy. The detector electronics decode the position of each photon event, and the decoding algorithm that associates a given event with the appropriate pixel is determined by the geometry of the anode array. The standard MAMA detector has a spatial resolution set by the anode array of 25 microns, but the MCP pore resolution exceeds this. The performance of a new algorithm that halves the pixel spacing and improves the pixel spatial resolution is described. The new algorithm does not degrade the pulse-pair resolution of the detector and does not require any modifications to the detector tube. Measurements of the detector's response demonstrate that high resolution decoding yields a 60 percent enhancement in spatial resolution. Measurements of the performance of the high resolution algorithm with a 14 micron MAMA detector are also described. The parameters that control high resolution performance are discussed. Results of the application of high resolution decoding to speckle interferometry are presented.

Kasle, David B.

Maximum-likelihood soft-decision decoding of block codes using the A* algorithm

The A* algorithm finds the path in a finite depth binary tree that optimizes a function. Here, it is applied to maximum-likelihood soft-decision decoding of block codes where the function optimized over the codewords is the likelihood function of the received sequence given each codeword. The algorithm considers codewords one bit at a time, making use of the most reliable received symbols first and pursuing only the partially expanded codewords that might be maximally likely. A version of the A* algorithm for maximum-likelihood decoding of block codes has been implemented for block codes up to 64 bits in length. The efficiency of this algorithm makes simulations of codes up to length 64 feasible. This article details the implementation currently in use, compares the decoding complexity with that of exhaustive search and Viterbi decoding algorithms, and presents performance curves obtained with this implementation of the A* algorithm for several codes.

Ekroot, L.

Circuit for high resolution decoding of multi-anode microchannel array detectors

A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

Kasle, David B.

Bit Error Probability for Maximum Likelihood Decoding of Linear Block Codes

In this paper, the bit error probability P(sub b) for maximum likelihood decoding of binary linear codes is investigated. The contribution of each information bit to P(sub b) is considered. For randomly generated codes, it is shown that the conventional approximation at high SNR P(sub b) is approximately equal to (d(sub H)/N)P(sub s), where P(sub s) represents the block error probability, holds for systematic encoding only. Also systematic encoding provides the minimum P(sub b) when the inverse mapping corresponding to the generator matrix of the code is used to retrieve the information sequence. The bit error performances corresponding to other generator matrix forms are also evaluated. Although derived for codes with a generator matrix randomly generated, these results are shown to provide good approximations for codes used in practice. Finally, for decoding methods which require a generator matrix with a particular structure such as trellis decoding or algebraic-based soft decision decoding, equivalent schemes that reduce the bit error probability are discussed.

Lin, Shu

Tail Biting Trellis Representation of Codes: Decoding and Construction

This paper presents two new iterative algorithms for decoding linear codes based on their tail biting trellises, one is unidirectional and the other is bidirectional. Both algorithms are computationally efficient and achieves virtually optimum error performance with a small number of decoding iterations. They outperform all the previous suboptimal decoding algorithms. The bidirectional algorithm also reduces decoding delay. Also presented in the paper is a method for constructing tail biting trellises for linear block codes.

Shao. Rose Y.

Concept for simplified serial digital decoder

Modular decoder, which lends itself best to special purpose digital equipment using sequential access memories, decodes the first order Reed-Muller codes. It functions as a maximum-likelihood exhaustive-search decoder and is a modular implementation to accommodate codes of any length.

Green, R. R.

Nonsystematic convolutional codes for sequential decoding in space applications.

Description of a class of rate 1/2 nonsystematic convolutional codes with the following desirable properties: (1) an undetected decoding error probability verified by simulation to be much smaller than for the best systematic codes of the same constraint length; (2) computation behavior with sequential decoding verified by simulation to be virtually identical to that of the best systematic codes; (3) a ?quick-look-in' feature that permits recovery of the information sequence from the hard-decisioned received data without decoding simply by modulo-two addition of the received sequences; and (4) suitability for encoding by simple circuitry requiring less hardware than encoders for the best systematic codes of the same constraint length. Theoretical analyses are given. These codes have been adopted for use in several forthcoming space missions.

Massey, J. L.

A flexible high-speed sequential decoder for deep space channels.

This paper describes a sequential decoding machine built at the Jet Propulsion Laboratory (JPL), which uses a 3-bit quantization of the code symbols and achieves a computation rate of MHz. This machine is flexible and can be programmed to decode any complementary convolutional code with rates down to 1/4 and constraint lengths up to 32. In addition, metric programmability is provided for optimization of decoder performance with respect to channel parameter variations.

Layland, J. W.

A high speed sequential decoder

The performance and theory of operation for the High Speed Hard Decision Sequential Decoder are delineated. The decoder is a forward error correction system which is capable of accepting data from binary-phase-shift-keyed and quadriphase-shift-keyed modems at input data rates up to 30 megabits per second. Test results show that the decoder is capable of maintaining a composite error rate of 0.00001 at an input E sub b/N sub o of 5.6 db. This performance has been obtained with minimum circuit complexity.

Lum, H., Jr.

Error-erasure decoding of product codes.

Two error-erasure decoding algorithms for product codes that correct all the error-erasure patterns guaranteed correctable by the minimum Hamming distance of the product code are given. The first algorithm works when at least one of the component codes is majority-logic decodable. The second algorithm works for any product code. Both algorithms use the decoders of the component codes.

Wainberg, S.

Comparison of rate one-half, equivalent constraint length 24, binary convolutional codes for use with sequential decoding on the deep-space channel

Virtually all previously-suggested rate 1/2 binary convolutional codes with KE = 24 are compared. Their distance properties are given; and their performance, both in computation and in error probability, with sequential decoding on the deep-space channel is determined by simulation. Recommendations are made both for the choice of a specific KE = 24 code as well as for codes to be included in future coding standards for the deep-space channel. A new result given in this report is a method for determining the statistical significance of error probability data when the error probability is so small that it is not feasible to perform enough decoding simulations to obtain more than a very small number of decoding errors.

Massey, J. L.

Command decoder unit

The design and testing of laboratory hardware (a command decoder unit) used in evaluating space shuttle instrumentation, data processing, and ground check-out operations is described. The hardware was a modification of another similar instrumentation system. A data bus coupler was designed and tested to interface the equipment to a central bus controller (computer). A serial digital data transfer mechanism was also designed. Redundant power supplies and overhead modules were provided to minimize the probability of a single component failure causing a catastrophic failure. The command decoder unit is packaged in a modular configuration to allow maximum user flexibility in configuring a system. Test procedures and special test equipment for use in testing the hardware are described. Results indicate that the unit will allow NASA to evaluate future software systems for use in space shuttles. The units were delivered to NASA and appear to be adequately performing their intended function. Engineering sketches and photographs of the command decoder unit are included.

Source record

Decoding with multipliers

A general technique, called decoding with multipliers, is presented that can be used to decode any linear code. The technique is applied to the (48,24) quadratic residue code and yields the first known practical decoding algorithm for this powerful code.

Baumert, L. D.

Concatenated coding systems employing a unit-memory convolutional code and a byte-oriented decoding algorithm

Concatenated coding systems utilizing a convolutional code as the inner code and a Reed-Solomon code as the outer code are considered. In order to obtain very reliable communications over a very noisy channel with relatively small coding complexity, it is proposed to concatenate a byte oriented unit memory convolutional code with an RS outer code whose symbol size is one byte. It is further proposed to utilize a real time minimal byte error probability decoding algorithm, together with feedback from the outer decoder, in the decoder for the inner convolutional code. The performance of the proposed concatenated coding system is studied, and the improvement over conventional concatenated systems due to each additional feature is isolated.

Lee, L. N.