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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

Programmable Logic Device (PLD) Design Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. At the conclusion of the development, the software and hardware description language (HDL) code was delivered to JSC for their use in their iPAS test bed to get hands-on experience with the STRS standard, and for development of their own STRS Waveforms on the now STRS compliant platform.The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe the design of the HDL code for the FPGA portion of the iPAS STRS Radio particularly the design of the FPGA wrapper and the test waveform.

VHDL↗
NASA NTRS2008

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
NASA NTRS1992

Design and performance comparison of fuzzy logic based tracking controllers

Several camera tracking controllers based on fuzzy logic principles have been designed and tested in software simulation in the software technology branch at the Johnson Space Center. The fuzzy logic based controllers utilize range measurement and pixel positions from the image as input parameters and provide pan and tilt gimble rate commands as output. Two designs of the rulebase and tuning process applied to the membership functions are discussed in light of optimizing performance. Seven test cases have been designed to test the performance of the controllers for proximity operations where approaches like v-bar, fly-around and station keeping are performed. The controllers are compared in terms of responsiveness, and ability to maintain the object in the field-of-view of the camera. Advantages of the fuzzy logic approach with respect to the conventional approach have been discussed in terms of simplicity and robustness.

Lea, Robert N.↗
DOE OSTI2024

NNSA MSIIP Intern Biweekly Report - #3

These couple of weeks I continued doing solvent tests with the 3D printed actuators. I made measurements and organized the data obtained from the tests. I was also able to get a logic gate design that worked according to the logic and was able to start printing and modifying the design. I've been understanding more about what parts of the design it would be best to modify and why certain ideas do not work versus others. I've been communicating with my mentor when I make edits to the design to ensure I keep moving forward with it and make it look closer and closer to what we need it to. I've continued to attend the seminars held by the department and learned more about the different methods of 3d printing and the different projects that are being worked on here.

36 MATERIALS SCIENCE↗
NASA NTRS1994

Structural Vibration Suppression Using Fuzzy Logic Control

This paper designs a fuzzy logic controller to suppress the vibrations of a large space antenna-like ground experimental structure located at the JPL/AFPL Large Spacecraft Control Laboratory.

fuzzy logic controller linear robust control fuzzy↗
NASA NTRS1986

Rdesign: A data dictionary with relational database design capabilities in Ada

Data Dictionary is defined to be the set of all data attributes, which describe data objects in terms of their intrinsic attributes, such as name, type, size, format and definition. It is recognized as the data base for the Information Resource Management, to facilitate understanding and communication about the relationship between systems applications and systems data usage and to help assist in achieving data independence by permitting systems applications to access data knowledge of the location or storage characteristics of the data in the system. A research and development effort to use Ada has produced a data dictionary with data base design capabilities. This project supports data specification and analysis and offers a choice of the relational, network, and hierarchical model for logical data based design. It provides a highly integrated set of analysis and design transformation tools which range from templates for data element definition, spreadsheet for defining functional dependencies, normalization, to logical design generator.

Lekkos, Anthony A.↗
NASA NTRS1985

Cable-catenary large antenna concept

Deployable to very large diameters (over 1000 ft), while still remaining compatible with a complete satellite system launch by STS, the cable-catenary antenna comprises: 8 radial deployable boom masts; a deployable hub and feed support center mast; balanced front and back, radial and circumferential catenary cabling for highly accurate (mm) surface control; no interfering cabling in the antenna field; and an RF reflecting mesh supported on the front catenaries. Illustrations show the antenna-satellite system deployed and stowed configurations; the antenna deployment sequence; the design analysis logic; the sizing analysis output, and typical parametric design data.

Akle, W.↗
NASA NTRS1993

Radiation hardened microprocessor for small payloads

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

Shah, Ravi↗
NASA NTRS1983

RS-232 communications analyzer module for HP-1602A logic analyzer

The design and construction of a simple ASCII analyzer is described. It was built to interface directly to a Hewlett-Packard 1602A logic state analyzer but the circuitry could easily be configured to operate with any logic analyzer. The design of the ASCII analyzer allows the use of all the trace and delay functions for the HF-1602A. The ASCII analyzer circuit utilizes two universal Asynchronous Receiver/Transmitters (UAR/Ts) to simultaneously examine both the transmit and receive serial data lines. Baud rates from 300 to 9600 bits per second are selectable with the externally mounted DIP switch. The unit requires no external power supply connection and all of the integrated circuits are CMOS for low power consumption.

Yost, S. R.↗
DOE OSTI2025

Innovative PLC Design for Optimized Potable Water Managment

My project here at Idaho National Laboratory (INL) was to work on Potable Water PLC Design (Programmable Logic Controllers). I was tasked in making a new panel design for the PLC system that will be moved from TRA BLDG 696 to TRA BLDG 608. This design needed to be updated since the old PLC system being about 20 years old. The manufacturer of the MicroLogix 1200 life expectancy showed it to be 10-20 years, and the system was discontinued in 2017. The new system we implemented was called CompactLogix Controller 5380, along with a new 24 VDC/10 Amp Power Supply. I made a design using Microsoft Visio, with the new material. But we needed to add it onto an Aluminum Panel that the system will be mounted onto, we need Unistrut’s for the aluminum panel to be mounted to. Some of the material we will still be using, like the R1 Alarm Relay, will be moving with the PLC system. The rest of the material will be new supplies that need to be updated systems, which the site is waiting for to complete the PLC system.

47 - OTHER INSTRUMENTATION↗