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Curve generator capable of producing precisely repeatable curve for any single-valued function of voltage versus time uses digital approach, implemented by means of clocked feedback shift register, large scale integrated circuit diode matrix comprising about 12,000 diodes, counter, and digital-to-analog converter.
Digital computer simulation of shift register pseudo-random noise generators
Binary to binary-coded decimal converter using single set of logic circuits notwithstanding number of shift register decades
Magnetic storage wire counter design principles are given. Magnetic storage wire was coupled with two phase propagational driver in manual set counter shift register. Time delay between magnetic counter domain insertion and corresponding output pulse provides counting functions.
The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.
A modulo-M counter (of clock pulses) is decomposed into parallel modulo-m sub i counters, where each m sub i is a prime power divisor of M. The modulo-p sub i counters are feedback shift registers which cycle through p sub i distinct states. By this organization, every possible nontrivial data frame subperiod and delayed subperiod may be derived. The number of clock pulses required to bring every modulo-p sub i counter to a respective designated state or count is determined by the Chinese remainder theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.
General purpose sequence generator which includes 35-stage field shift register determines mathematical properties of polynomials such as divisibility, period, order of roots, and other parameters that effect desirability of various sequences for specific applications; for example, irreducible polynomials which characterize sequences with randomness properties.
A shielded integrated complimentary MOS transistor structure is described which is used to prevent field inversion in the region not occupied by the gates and which permits the use of a thinner field oxide, reduces the chip area, and has provision for simplified multilayer connections. The structure is used in the design of a static shift register and results in a 20% reduction in area.
The fabrication yield of an on-chip modifiable redundant circuit design for a 100M bit serial shift register is evaluated. The yield model is a redundancy design in which there is a primary loop and a set of secondary loops which can be enabled/disabled without introducing blanks to the data stream. This function has a finite yield, the loop-modification yield factor, which must be greater than 0.9 to make the system more economical than the simple nonredundant design. It is further established that small loop capacities greatly degrade the yield because of the effect of the modification yield factor, while large loop capacities degrade the yield because of defects in the operating area. As the modification yield increases the optimum loop capacity decreases. An optimum value for the number of redundant loops exists for each loop capacity. Other factors that affect the yield are the garnet film and the processed circuit.
Real-time Fourier analysis is provided by "bucket brigade' charge-transfer shift register. Device is small, inexpensive integrated circuit which does analog-to-digital-to-analog conversion, data processing, and time delay.
A system capable of generating every possible data frame subperiod and delayed subperiod of a data frame of length of M clock pulse intervals (CPIs) comprised of parallel modulo-m sub i counters is presented. Each m sub i is a prime power divisor of M and a cascade of alpha sub i identical modulo-p sub i counters. The modulo-p sub i counters are feedback shift registers which cycle through p sub i distinct states. Every possible nontrivial data frame subperiod and delayed subperiod is derived and a specific CPI in the data frame is detected. The number of clock pulses required to bring every modulo-p sub i counter to a respective designated state or count is determined by the Chinese remainder theorem. This corresponds to the solution of simultaneous congruences over relatively prime moduli.
We have successfully fabricated, tested, and operated a digital image tube consisting of a magnetically focused image intensifier tube in which a self-scanned linear array of 1024 silicon photodiodes operating in the EBS mode serves as the photoelectron image detector, amplifier, and intermediate image storage device. Integral on-chip MOS shift registers driven by an external clock sequentially interrogate the photodiodes through MOS FET multiplex switch arrays. Each output frame is a sequence of 256 analog pulses on each of four video lines. Laboratory and observing tests show that the output signal is photoelectron shot noise limited over at least a range of 1-100,000 detected photoelectrons per picture element, indicating that single photon detection is achieved. High-resolution astronomical spectroscopy has been carried out in the coude spectrograph of the 2.7-m telescope at McDonald Observatory. Examples are shown.
Circuit includes serial-in/parallel-out shift register and weighting network that are used to eliminate effects of noise and other nonrepetitive circuit transients. Register and weighting network average decisions from section of signal where decisions are more dependable or where differences between two consecutive samples are larger.
Modification of conventional digital counting filter is designed to store all possible combinations of filter coefficients in random access memory. Filter includes analog-to-digital coverter, X shift register, memory, accumulator, and digital-to-analog converter.
Self-aligned polysilicon gate technology was applied to double-diffused MOS (DMOS) construction in a manner that retains processing simplicity and effectively eliminates parasitic overlap capacitance because of the self-aligning feature. Depletion mode load devices with the same dimensions as the DMOS transistors were integrated. The ratioless feature results in smaller dimension load devices, allowing for higher density integration with no increase in the processing complexity of standard MOS technology. A number of inverters connected as ring oscillators were used as a vehicle to test the performance and to verify the anticipated benefits. The propagation time-power dissipation product and process related parameters were measured and evaluated. This report includes (1) details of the process; (2) test data and design details for the DMOS transistor, the load device, the inverter, the ring oscillator, and a shift register with a novel tapered geometry for the output stages; and (3) an analytical treatment of the effect of the distributed silicon gate resistance and capacitance on the speed of DMOS transistors.
The results are presented of a study on the use of the delta modulator as a digital encoder of television signals. The computer simulation of different delta modulators was studied in order to find a satisfactory delta modulator. After finding a suitable delta modulator algorithm via computer simulation, the results were analyzed and then implemented in hardware to study its ability to encode real time motion pictures from an NTSC format television camera. The effects of channel errors on the delta modulated video signal were tested along with several error correction algorithms via computer simulation. A very high speed delta modulator was built (out of ECL logic), incorporating the most promising of the correction schemes, so that it could be tested on real time motion pictures. Delta modulators were investigated which could achieve significant bandwidth reduction without regard to complexity or speed. The first scheme investigated was a real time frame to frame encoding scheme which required the assembly of fourteen, 131,000 bit long shift registers as well as a high speed delta modulator. The other schemes involved the computer simulation of two dimensional delta modulator algorithms.
A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications.
Correlation criteria have previously been established for identifying whether a given binary sequence would be a good frame sync word for phase-shift keyed telemetry. In the past, the search for a good K-bit sync word has involved the application of these criteria to the entire set of 2 exponent K binary K-tuples. It is shown that restricting this search to a much smaller subset consisting of K-bit prefixes of pseudonoise sequences results in sync words of comparable quality, with greatly reduced computer search times for larger values of K. As an example, this procedure is used to find good sync words of length 16-63; from a storage viewpoint, each of these sequences can be generated by a 5- or 6-bit linear feedback shift register.