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NASA NTRS2009

Digital Beamforming Scatterometer

This paper discusses scatterometer measurements collected with multi-mode Digital Beamforming Synthetic Aperture Radar (DBSAR) during the SMAP-VEX 2008 campaign. The 2008 SMAP Validation Experiment was conducted to address a number of specific questions related to the soil moisture retrieval algorithms. SMAP-VEX 2008 consisted on a series of aircraft-based.flights conducted on the Eastern Shore of Maryland and Delaware in the fall of 2008. Several other instruments participated in the campaign including the Passive Active L-Band System (PALS), the Marshall Airborne Polarimetric Imaging Radiometer (MAPIR), and the Global Positioning System Reflectometer (GPSR). This campaign was the first SMAP Validation Experiment. DBSAR is a multimode radar system developed at NASA/Goddard Space Flight Center that combines state-of-the-art radar technologies, on-board processing, and advances in signal processing techniques in order to enable new remote sensing capabilities applicable to Earth science and planetary applications [l]. The instrument can be configured to operate in scatterometer, Synthetic Aperture Radar (SAR), or altimeter mode. The system builds upon the L-band Imaging Scatterometer (LIS) developed as part of the RadSTAR program. The radar is a phased array system designed to fly on the NASA P3 aircraft. The instrument consists of a programmable waveform generator, eight transmit/receive (T/R) channels, a microstrip antenna, and a reconfigurable data acquisition and processor system. Each transmit channel incorporates a digital attenuator, and digital phase shifter that enables amplitude and phase modulation on transmit. The attenuators, phase shifters, and calibration switches are digitally controlled by the radar control card (RCC) on a pulse by pulse basis. The antenna is a corporate fed microstrip patch-array centered at 1.26 GHz with a 20 MHz bandwidth. Although only one feed is used with the present configuration, a provision was made for separate corporate feeds for vertical and horizontal polarization. System upgrades to dual polarization are currently under way. The DBSAR processor is a reconfigurable data acquisition and processor system capable of real-time, high-speed data processing. DBSAR uses an FPGA-based architecture to implement digitally down-conversion, in-phase and quadrature (I/Q) demodulation, and subsequent radar specific algorithms. The core of the processor board consists of an analog-to-digital (AID) section, three Altera Stratix field programmable gate arrays (FPGAs), an ARM microcontroller, several memory devices, and an Ethernet interface. The processor also interfaces with a navigation board consisting of a GPS and a MEMS gyro. The processor has been configured to operate in scatterometer, Synthetic Aperture Radar (SAR), and altimeter modes. All the modes are based on digital beamforming which is a digital process that generates the far-field beam patterns at various scan angles from voltages sampled in the antenna array. This technique allows steering the received beam and controlling its beam-width and side-lobe. Several beamforming techniques can be implemented each characterized by unique strengths and weaknesses, and each applicable to different measurement scenarios. In Scatterometer mode, the radar is capable to.generate a wide beam or scan a narrow beam on transmit, and to steer the received beam on processing while controlling its beamwidth and side-lobe level. Table I lists some important radar characteristics

Rincon, Rafael F.↗
NASA NTRS2007

A Low-Complexity Circuit for On-Sensor Concurrent A/D Conversion and Compression

A low-complexity circuit for on-sensor compression is presented. The proposed circuit achieves complexity savings by combining a single-slope analog-to-digital converter with a Golomb-Rice entropy encoder and by implementing a low-complexity adaptation rule. The adaptation rule monitors the output codewords and minimizes their length by incrementing or decrementing the value of the Golomb-Rice coding parameter k. Its hardware implementation is one order of magnitude lower than existing adaptive algorithms. The compression circuit has been fabricated using a 0.35 micrometers CMOS technology and occupies an area of 0.0918 mm2. Test measurements confirm the validity of the design

Leon-Salas, Walter D.↗
NASA NTRS1993

Total Ionizing Dose Effects in 12-Bit Successive-Approximation Analog-To-Digital Converters

Analog-to-digital (A/D) converters are critical components in many space and military systems, and there have been numerous advances in A/D converter technology that have increased the resolution and conversion time. The increased performance is due to two factors: (1) advances in circuit design and complexity, which have increased the number of components and the integration density; and (2) new process technologies, such as BiCMOS, which provide better performance, cost, and smaller size in mixed-signal circuits. High-speed A/D converters, with conversion rates above 1 MHz, present a challenge to circuit designers and test engineers. Their complex architectures and high-performance specifications result in numerous possible failure modes when they are subjected to ionizing radiation. The dominant failure mode may depend on the specific application because the fundamental effects on MOS and bipolar transistors are strongly affected by bias conditions.

Lee, C. I.↗
NASA NTRS1994

Using Commercial Off-the-Shelf Software Tools for Space Shuttle Scientific Software

In October 1993, the Astronaut Science Advisor (ASA) was on board the STS-58 flight of the space shuttle. ASA is an interactive system providing data acquisition and analysis, experiment step re-scheduling, and various other forms of reasoning. As fielded, the system runs on a single Macintosh PowerBook 170, which hosts the six ASA modules. There is one other piece of hardware, an external (GW Instruments, Sommerville, Massachusetts) analog-to-digital converter connected to the PowerBook's SCSI port. Three main software tools were used: LabVIEW, CLIPS, and HyperCard: First, a module written in LabVIEW (National Instruments, Austin, Texas) controls the A/D conversion and stores the resulting data in appropriate arrays. This module also analyzes the numerical data to produce a small set of characteristic numbers or symbols describing the results of an experiment trial. Second, a forward-chaining inference system written in CLIPS (NASA) uses the symbolic information provided by the first stage with a static rule base to infer decisions about the experiment. This expert system shell is used by the system for diagnosis. The third component of the system is the user interface, written in HyperCard (Claris Inc. and Apple Inc., both in Cupertino, California).

Groleau, Nicolas↗
NASA NTRS1993

Reconfigurable fuzzy cell

This invention relates to a reconfigurable fuzzy cell comprising a digital control programmable gain operation amplifier, an analog-to-digital converter, an electrically erasable PROM, and 8-bit counter and comparator, and supporting logic configured to achieve in real-time fuzzy systems high throughput, grade-of-membership or membership-value conversion of multi-input sensor data. The invention provides a flexible multiplexing-capable configuration, implemented entirely in hardware, for effectuating S-, Z-, and PI-membership functions or combinations thereof, based upon fuzzy logic level-set theory. A membership value table storing 'knowledge data' for each of S-, Z-, and PI-functions is contained within a nonvolatile memory for storing bits of membership and parametric information in a plurality of address spaces. Based upon parametric and control signals, analog sensor data is digitized and converted into grade-of-membership data. In situ learn and recognition modes of operation are also provided.

Salazar, George A.↗
NASA NTRS1996

Progress in Voltage and Current Mode On-Chip Analog-to-Digital converters for CMOS Image Sensors

Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 ??itch in a 1.2 ??-well CMOS process and a 40 ??itch in a 2 ??-well CMOS process. The successive approximation designs consume as little as 49 ??t a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental sigma-delta ADC test chips designed to be multiplied among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 ??t a 5 KHz.

analog-to-digital↗
NASA NTRS2001

Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

Gerber, Scott S.↗
NASA NTRS2011

Fiber-Optic Magnetic-Field-Strength Measurement System for Lightning Detection

A fiber-optic sensor system is designed to measure magnetic fields associated with a lightning stroke. Field vector magnitudes are detected and processed for multiple locations. Since physical limitations prevent the sensor elements from being located in close proximity to highly conductive materials such as aluminum, the copper wire sensor elements (3) are located inside a 4-cubic-in. (.66-cubic-cm) plastic housing sensor head and connected to a fiber-optic conversion module by shielded cabling, which is limited to the shortest length feasible. The signal path between the conversion module and the avionics unit which processes the signals are fiber optic, providing enhanced immunity from electromagnetic radiation incident in the vicinity of the measurements. The sensors are passive, lightweight, and much smaller than commercial B-dot sensors in the configuration which measures a three-dimensional magnetic field. The system is expandable, and provides a standard-format output signal for downstream processing. Inside of the sensor head, three small search coils, each having a few turns on a circular form, are mounted orthogonally inside the non-metallic housing. The fiber-optic conversion module comprises three interferometers, one for each search coil. Each interferometer has a high bandwidth optical phase modulator that impresses the signal received from its search coil onto its output. The output of each interferometer travels by fiber optic cable to the avionics unit, and the search coil signal is recovered by an optical phase demodulator. The output of each demodulator is fed to an analog-to-digital converter, whose sampling rate is determined by the maximum expected rate of rise and peak signal magnitude. The output of the digital processor is a faithful reproduction of the coil response to the incident magnetic field. This information is provided in a standard output format on a 50-ohm port that can be connected to any number of data collection and processing instruments and/or systems. The measurement of magnetic fields using fiber-optic signal processing is novel because it eliminates limitations of a traditional B-dot system. These limitations include the distance from the sensor to the measurement device, the potential for the signal to degrade or be corrupted by EMI from lightning, and the size and weight of the sensor and associated plate.

Gurecki, Jay↗
NASA NTRS1995

Resonant Tunneling Analog-To-Digital Converter

As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.

Broekaert, T. P. E.↗
NASA NTRS1972

An improved data transfer and storage technique for hybrid computation

Improved technique was developed for transferring and storing data at faster than real time speeds on hybrid computer. Predominant advantage is combined use of electronic relays, track and store units, and analog-to-digital and digital-to-analog conversion units of hybrid computer.

Hansing, A. M.↗
NASA NTRS1981

Minus 55 to plus 200 deg C 12 bit analog-to-digital converter

A 12 bit successive approximation analog to digital converter that offers moderately high speed precision data conversion at a reasonable level of cost and complexity is studied. The ADCH10HT extends this capability over a temperature range of -55 to +200 C. No missing-code performance is maintained over the entire temperature range. The converter is completely self-contained with internal clock and +10 volt reference. The CMOS devices offer low power dissipation, so that the internal temperature of the hybrid circuit does not rise as much from self heating. In CMOS circuits, pn junction leakage currents are returned to the supplies so that the logic keeps working at temperatures up to 250 C.

Smith, L. R.↗
NASA NTRS1993

Analog-To-Digital Converter For Sum-Of-Squares Measurements

Analog-to-digital converter (ADC) circuit designed as part of larger circuit intended to measure root-mean-square current on 20-kHz powerline. Provides digital output of 11 bits of data plus 1-bit overflow signal at sampling rate of 4 MHz. Output processed by multiplying-and-accumulating circuitry to obtain sum of squares and digitized current samples accumulated during preset number of consecutive sampling periods. Used to digitize current samples from ADC directly as alternative or auxiliary output. Notable features include low power and fast conversion.

Osborn, Stephen H.↗
NASA NTRS1991

Compensated digital readout family

ISC has completed test on an IC which has 32 channels of amplifiers, low pass anti-aliasing filters, 13-bit analog-to-digital (A/D) converters with non-uniformity correction per channel and a digital multiplexer. The single slope class of A/D conversion is described, as are the unique variations required for incorporation of this technique for use with on-focal plane detector readout electronics. This paper describes the architecture used to implement the digital on-focal plane signal processing functions. Results from measured data on a test IC are presented for a circuit containing these functions operating at a sensor frame rate of 1000 hertz.

Ludwig, David E.↗
NASA NTRS1993

An Integrated Imaging Detector of Polarization and Spectral Content

A new type of image detector has been designed to simultaneously analyze the polarization of light at all picture elements in a scene. The Integrated Dual Imaging Detector (IDID) consists of a polarizing beamsplitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. It should be capable of 1:10(exp 4) polarization discrimination. The IDID should simplify the design and operation of imaging polarimeters and spectroscopic imagers used, for example, in atmospheric and solar research. Innovations in the IDID include (1) two interleaved 512 x 1024-pixel imaging arrays (one for each polarization plane); (2) large dynamic range (well depth of 10(exp 6) electrons per pixel); (3) simultaneous readout of both images at 10 million pixels per second each; (4) on-chip analog signal processing to produce polarization maps in real time; (5) on-chip 10-bit A/D conversion. When used with a lithium-niobate Fabry-Perot etalon or other color filter that can encode spectral information as polarization, the IDID can collect and analyze simultaneous images at two wavelengths. Precise photometric analysis of molecular or atomic concentrations in the atmosphere is one suggested application. When used in a solar telescope, the IDID will charge the polarization, which can then be converted to maps of the vector magnetic fields on the solar surface.

Rust, D. M.↗
NASA NTRS2007

Miniature L-Band Radar Transceiver

A miniature L-band transceiver that operates at a carrier frequency of 1.25 GHz has been developed as part of a generic radar electronics module (REM) that would constitute one unit in an array of many identical units in a very-large-aperture phased-array antenna. NASA and the Department of Defense are considering the deployment of such antennas in outer space; the underlying principles of operation, and some of those of design, also are applicable on Earth. The large dimensions of the antennas make it advantageous to distribute radio-frequency electronic circuitry into elements of the arrays. The design of the REM is intended to implement the distribution. The design also reflects a requirement to minimize the size and weight of the circuitry in order to minimize the weight of any such antenna. Other requirements include making the transceiver robust and radiation-hard and minimizing power demand. Figure 1 depicts the functional blocks of the REM, including the L-band transceiver. The key functions of the REM include signal generation, frequency translation, amplification, detection, handling of data, and radar control and timing. An arbitrary-waveform generator that includes logic circuitry and a digital-to-analog converter (DAC) generates a linear-frequency-modulation chirp waveform. A frequency synthesizer produces local-oscillator signals used for frequency conversion and clock signals for the arbitrary-waveform generator, for a digitizer [that is, an analog-to-digital converter (ADC)], and for a control and timing unit. Digital functions include command, timing, telemetry, filtering, and high-rate framing and serialization of data for a high-speed scientific-data interface. The aforementioned digital implementation of filtering is a key feature of the REM architecture. Digital filters, in contradistinction to analog ones, provide consistent and temperature-independent performance, which is particularly important when REMs are distributed throughout a large array. Digital filtering also enables selection among multiple filter parameters as required for different radar operating modes. After digital filtering, data are decimated appropriately in order to minimize the data rate out of an antenna panel. The L-band transceiver (see Figure 2) includes a radio-frequency (RF)-to-baseband down-converter chain and an intermediate- frequency (IF)-to-RF up-converter chain. Transmit/receive (T/R) switches enable the use of a single feed to the antenna for both transmission and reception. The T/R switches also afford a built-in test capability by enabling injection of a calibration signal into the receiver chain. In order of decreasing priority, components of the transceiver were selected according to requirements of radiation hardness, then compactness, then low power. All of the RF components are radiation-hard. The noise figure (NF) was optimized to the extent that (1) a low-noise amplifier (LNA) (characterized by NF < 2 dB) was selected but (2) the receiver front-end T/R switches were selected for a high degree of isolation and acceptably low loss, regardless of the requirement to minimize noise.

McWatters, Dalia↗
NASA NTRS2006

Digital Front End for Wide-Band VLBI Science Receiver

An upgrade to the very-long-baseline-interferometry (VLBI) science receiver (VSR) a radio receiver used in NASA's Deep Space Network (DSN) is currently being implemented. The current VSR samples standard DSN intermediate- frequency (IF) signals at 256 MHz and after digital down-conversion records data from up to four 16-MHz baseband channels. Currently, IF signals are limited to the 265-to-375-MHz range, and recording rates are limited to less than 80 Mbps. The new digital front end, denoted the Wideband VSR, provides improvements to enable the receiver to process wider bandwidth signals and accommodate more data channels for recording. The Wideband VSR utilizes state-of-the-art commercial analog-to-digital converter and field-programmable gate array (FPGA) integrated circuits, and fiber-optic connections in a custom architecture. It accepts IF signals from 100 to 600 MHz, sampling the signal at 1.28 GHz. The sample data are sent to a digital processing module, using a fiber-optic link for isolation. The digital processing module includes boards designed around an Advanced Telecom Computing Architecture (ATCA) industry-standard backplane. Digital signal processing implemented in FPGAs down-convert the data signals in up to 16 baseband channels with programmable bandwidths from 1 kHz to 16 MHz. Baseband samples are transmitted to a computer via multiple Ethernet connections allowing recording to disk at rates of up to 1 Gbps.

Jongeling, Andre↗
NASA NTRS2013

Mixed Linear/Square-Root Encoded Single-Slope Ramp Provides Low-Noise ADC with High Linearity for Focal Plane Arrays

Single-slope analog-to-digital converters (ADCs) are particularly useful for onchip digitization in focal plane arrays (FPAs) because of their inherent monotonicity, relative simplicity, and efficiency for column-parallel applications, but they are comparatively slow. Squareroot encoding can allow the number of code values to be reduced without loss of signal-to-noise ratio (SNR) by keeping the quantization noise just below the signal shot noise. This encoding can be implemented directly by using a quadratic ramp. The reduction in the number of code values can substantially increase the quantization speed. However, in an FPA, the fixed pattern noise (FPN) limits the use of small quantization steps at low signal levels. If the zero-point is adjusted so that the lowest column is onscale, the other columns, including those at the center of the distribution, will be pushed up the ramp where the quantization noise is higher. Additionally, the finite frequency response of the ramp buffer amplifier and the comparator distort the shape of the ramp, so that the effective ramp value at the time the comparator trips differs from the intended value, resulting in errors. Allowing increased settling time decreases the quantization speed, while increasing the bandwidth increases the noise. The FPN problem is solved by breaking the ramp into two portions, with some fraction of the available code values allocated to a linear ramp and the remainder to a quadratic ramp. To avoid large transients, both the value and the slope of the linear and quadratic portions should be equal where they join. The span of the linear portion must cover the minimum offset, but not necessarily the maximum, since the fraction of the pixels above the upper limit will still be correctly quantized, albeit with increased quantization noise. The required linear span, maximum signal and ratio of quantization noise to shot noise at high signal, along with the continuity requirement, determines the number of code values that must be allocated to each portion. The distortion problem is solved by using a lookup table to convert captured code values back to signal levels. The values in this table will be similar to the intended ramp value, but with a correction for the finite bandwidth effects. Continuous-time comparators are used, and their bandwidth is set below the step rate, which smoothes the ramp and reduces the noise. No settling time is needed, as would be the case for clocked comparators, but the low bandwidth enhances the distortion of the non-linear portion. This is corrected by use of a return lookup table, which differs from the one used to generate the ramp. The return lookup table is obtained by calibrating against a stepped precision DC reference. This results in a residual non-linearity well below the quantization noise. This method can also compensate for differential non-linearity (DNL) in the DAC used to generate the ramp. The use of a ramp with a combination of linear and quadratic portions for a single-slope ADC is novel. The number of steps is minimized by keeping the step size just below the photon shot noise. This in turn maximizes the speed of the conversion. High resolution is maintained by keeping small quantization steps at low signals, and noise is minimized by allowing the lowest analog bandwidth, all without increasing the quantization noise. A calibrated return lookup table allows the system to maintain excellent linearity.

Wrigley, Chris J.↗