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At least 109 records · Page 6

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistors

The threshold voltages of a carbon nanotube (CNT) field-effect transistor (FET) are derived and compared with those of the metal oxide-semiconductor (MOS) FETs. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, which is the CNT diameter direction, and this makes the CNTFET characteristics quite different from those in MOSFETs. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and it is shown that the familiar relations are still valid because of the macroscopic number of states available in the CNTs. This is in sharp contrast to the cases of quantum dots. Using these relations, we derive an inversion threshold voltage V(sub Ti) and an accumulation threshold voltage V(sub Ta) as a function of the Fermi level E(sub F) in the channel, where E(sub F) is a measure of channel doping. V(sub Ti) of the CNTFETs has a much stronger dependence than that of MOSFETs, while V(sub Ta)s of both CNTFETs and MOSFETs depend quite weakly on E(sub F) with the same functional form. This means the transition from normally-off mode to normally-on mode is much sharper in CNTFETs as the doping increases, and this property has to be taken into account in circuit design.

Yamada, Toshishige↗

Efficient Design in a DC to DC Converter Unit

Space Flight hardware requires high power conversion efficiencies due to limited power availability and weight penalties of cooling systems. The International Space Station (ISS) Electric Power System (EPS) DC-DC Converter Unit (DDCU) power converter is no exception. This paper explores the design methods and tradeoffs that were utilized to accomplish high efficiency in the DDCU. An isolating DC to DC converter was selected for the ISS power system because of requirements for separate primary and secondary grounds and for a well-regulated secondary output voltage derived from a widely varying input voltage. A flyback-current-fed push-pull topology or improved Weinberg circuit was chosen for this converter because of its potential for high efficiency and reliability. To enhance efficiency, a non-dissipative snubber circuit for the very-low-Rds-on Field Effect Transistors (FETs) was utilized, redistributing the energy that could be wasted during the switching cycle of the power FETs. A unique, low-impedance connection system was utilized to improve contact resistance over a bolted connection. For improved consistency in performance and to lower internal wiring inductance and losses a planar bus system is employed. All of these choices contributed to the design of a 6.25 KW regulated dc to dc converter that is 95 percent efficient. The methodology used in the design of this DC to DC Converter Unit may be directly applicable to other systems that require a conservative approach to efficient power conversion and distribution.

Bruemmer, Joel E.↗

Single Event Effects Testing of the Linfinity SG1525A Pulse Width Modulator Controller

Pulse Width Modulator (PWM) Controllers are the heart of switching power supply systems in development today. The PWMs considered here have the same integration advantages as many other controllers but it also includes the interface drivers for the follow-on power Field Effect Transistors (FET). Previous work on these types of devices looked into the required test methodologies [ 11 and the impact of radiation on the soft start and shutdown circuits of typically incorporated in the technology [2]. Taking advantage of this previous work this study was undertaken to determine the single event destructive and transient susceptibility of the Linfinity SG1525A Pulse Width Modulator Controller. The device was monitored for transient interruptions in the output signals and for destructive events induced by exposing it to a heavy ion beam at the Texas A&M University Cyclotron Single Event Effects Test Facility. After exposing these devices to the beam, a new upset mode has been identified that can lead to catastrophic power supply system failure if this event would occur while drive power FETs off the two device outputs. The devices and the test methods used will be described first. This will be followed by a brief description of the data collected to date (not all data can be presented with the length constraints of the summary) and a summary of the key results.

Howard, J. W., Jr.↗

Electrospun Polyaniline/Polyethylene Oxide Nanofiber Field Effect Transistor

We report on the observation of field effect transistor (FET) behavior in electrospun camphorsulfonic acid doped polyaniline(PANi)/polyethylene oxide(PE0) nanofibers. Saturation channel currents are observed at surprisingly low source/drain voltages. The hole mobility in the depletion regime is 1.4 x 10(exp -4) sq cm/V s while the 1-D charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx. 10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating 1-D polymer FET's.

Pinto, N. J.↗

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Demonstrated

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decisionmaking ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline/polyethylene oxide (PANi/PEO) nanofibers are of interest because they have electrical conductivities that can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain. At the NASA Glenn Research Center, we have observed field effect transistor (FET) behavior in electrospun PANi/PEO nanofibers doped with camphorsulfonic acid. The nanofibers were deposited onto Au electrodes, which had been prepatterned onto oxidized silicon substrates. The preceding scanning electron image shows the device used in the transistor measurements. Saturation channel currents are observed at surprisingly low source/drain voltages (see the following graph). The hole mobility in the depletion regime is 1.4x10(exp -4)sq cm/V sec, whereas the one-dimensional charge density (at zero gate bias) is calculated to be approximately 1 hole per 50 two-ring repeat units of polyaniline, consistent with the rather high channel conductivity (approx.10(exp -3) S/cm). Reducing or eliminating the PEO content in the fiber is expected to enhance device parameters. Electrospinning is thus proposed as a simple method of fabricating one-dimensional polymer FET's.

Mueller, Carl H.↗

Improved Signal Chains for Readout of CMOS Imagers

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Pain, Bedabrata↗

Disabling CNT Electronic Devices by Use of Electron Beams

Bombardment with tightly focused electron beams has been suggested as a means of electrically disabling selected individual carbon-nanotubes (CNTs) in electronic devices. Evidence in support of the suggestion was obtained in an experiment in which a CNT field-effect transistor was disabled (see figure) by focusing a 1-keV electron beam on a CNT that served as the active channel of a field-effect transistor (FET). Such bombardment could be useful in the manufacture of nonvolatile-memory circuits containing CNT FETs. Ultimately, in order to obtain the best electronic performances in CNT FETs and other electronic devices, it will be necessary to fabricate the devices such that each one contains only a single CNT as an active element. At present, this is difficult because there is no way to grow a single CNT at a specific location and with a specific orientation. Instead, the common practice is to build CNTs into electronic devices by relying on spatial distribution to bridge contacts. This practice results in some devices containing no CNTs and some devices containing more than one CNT. Thus, CNT FETs have statistically distributed electronic characteristics (including switching voltages, gains, and mixtures of metallic and semiconducting CNTs). According to the suggestion, by using a 1-keV electron beam (e.g., a beam from a scanning electron microscope), a particular nanotube could be rendered electrically dysfunctional. This procedure could be repeated as many times as necessary on different CNTs in a device until all of the excess CNTs in the device had been disabled, leaving only one CNT as an active element (e.g., as FET channel). The physical mechanism through which a CNT becomes electrically disabled is not yet understood. On one hand, data in the literature show that electron kinetic energy >86 keV is needed to cause displacement damage in a CNT. On the other hand, inasmuch as a 1-keV beam focused on a small spot (typically a few tens of nanometers wide) deposits a significant amount of energy in a small volume, the energy density may suffice to thermally induce structural and/or electronic changes that disable the CNT. Research may be warranted to investigate this effect in detail.

Petkov, Mihail↗

Zinc Alloys for the Fabrication of Semiconductor Devices

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Ryu, Yungryel↗

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Choi, Sang↗

Multiloop Rapid-Rise/Rapid Fall High-Voltage Power Supply

A proposed multiloop power supply would generate a potential as high as 1.25 kV with rise and fall times <100 s. This power supply would, moreover, be programmable to generate output potentials from 20 to 1,250 V and would be capable of supplying a current of at least 300 A at 1,250 V. This power supply is intended to be a means of electronic shuttering of a microchannel plate that would be used to intensify the output of a charge-coupled-device imager to obtain exposure times as short as 1 ms. The basic design of this power supply could also be adapted to other applications in which high voltages and high slew rates are needed. At the time of reporting the information for this article, there was no commercially available power supply capable of satisfying the stated combination of voltage, rise-time, and fall-time requirements. The power supply would include a preregulator that would be used to program a voltage 1/30 of the desired output voltage. By means of a circuit that would include a pulse-width modulator (PWM), two voltage doublers, and a transformer having two primary and two secondary windings, the preregulator output voltage would be amplified by a factor of 30. A resistor would limit the current by controlling a drive voltage applied to field-effect transistors (FETs) during turn-on of the PWM. Two feedback loops would be used to regulate the high output voltage. A pulse transformer would be used to turn on four FETs to short-circuit output capacitors when the outputs of the PWM were disabled. Application of a 0-to-5-V square to a PWM shut-down pin would cause a 20-to-1,250-V square wave to appear at the output.

Bearden, Douglas↗

Maintaining Stability During a Conducted-Ripple EMC Test

An improved technique, and electronic circuitry to implement the technique, have been developed for a military-standard electromagnetic-compatibility (EMC) test in which one analyzes susceptibility to low-frequency ripple conducted into the equipment under test via a DC power line. In the traditional technique for performing the particular test, the ripple is coupled onto the DC power line via a transformer. Depending upon some design details of the equipment under test, the inductance of the transformer can contribute a degree of instability that results in an oscillation of amplitude large enough to destroy the equipment. It is usually possible to suppress the oscillation by connecting a damping resistor to the primary terminals of the ripple-injection transformer. However, it is important to emphasize the usually in the preceding sentence: sometimes, the resistive damping becomes insufficient to suppress destructive oscillation. In addition, undesirably, the resistor contributes to power dissipation and power demand, and thereby also necessitates the use of a larger ripple voltage amplifier. Yet another disadvantage of the transformer-coupling technique is that the transformer introduces low-frequency distortion of the injected ripple voltage. The improved technique makes it possible to inject ripple with very low distortion at low frequency, without inducing oscillation. In this technique, a transformer is not used: Instead, power is fed to the equipment under test via series power field-effect transistors (FETs) controlled by a summing operational amplifier. One of the inputs to the amplifier controls the DC component of the power-line voltage; the other input, generated by an external oscillator, controls the ripple component. The circuitry for implementing this technique includes panel displays, an internal power supply for the operational amplifier and panel displays, and amplitude controls for the DC and ripple powerline voltage components.

Vorperian, Vatche↗

High-Voltage Power Supply With Fast Rise and Fall Times

A special-purpose high-voltage power supply can be electronically switched on and off with fast rise and fall times, respectively. The output potential is programmable from 20 to 1,250 V. An output current of 50 A can be sustained at 1,250 V. The power supply was designed specifically for electronically shuttering a microchannel plate in an x-ray detector that must operate with exposure times as short as 1 ms. The basic design of the power supply is also adaptable to other applications in which there are requirements for rapid slewing of high voltages. The power-supply circuitry (see figure) includes a preregulator, which is used to program the output at 1/30 of the desired output potential. After the desired voltage has been set, the outputs of a pulse width modulator (PWM) are enabled and used to amplify the preregulator output potential by 30. The amplification is achieved by use of two voltage doublers with a transformer that has two primary and two secondary windings. A resistor is used to limit the current by controlling the drive voltage of two field-effect transistors (FETs) during turn-on of the PWM. A pulse transformer is used to turn on four FETs to short-circuit four output capacitors when the outputs of the PWM have been disabled. The most notable aspects of the performance of the power supply are a rise time of only 80 s and a fall time of only 60 s at a load current of 50 A or less. Another notable aspect is that the application of a 0-to-5-V square wave to a shutdown pin of the PWM causes the production of a 0-to-1,250-V square wave at the output terminals.

Bearden, Douglas B.↗

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗

Radiation and Thermal Cycling Effects on EPC1001 Gallium Nitride Power Transistors

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These include radiation, extreme temperatures, and thermal cycling, to name a few. Information pertaining to performance of electronic parts and systems under hostile environments is very scarce, especially for new devices. Such data is very critical so that proper design is implemented in order to ensure mission success and to mitigate risks associated with exposure of on-board systems to the operational environment. In this work, newly-developed enhancement-mode field effect transistors (FET) based on gallium nitride (GaN) technology were exposed to various particles of ionizing radiation and to long-term thermal cycling over a wide temperature range. Data obtained on control (un-irradiated) and irradiated samples of these power transistors are presented and the results are discussed.

Patterson, Richard L.↗

Fully Printed, Flexible, Phased Array Antenna for Lunar Surface Communication

NASAs future exploration missions focus on the manned exploration of the Moon, Mars, and beyond, which will rely heavily on the development of a reliable communications infrastructure from planetary surface-to-surface, surface-to-orbit, and back to Earth. Flexible antennas are highly desired in many scenarios. Active phased array antennas (active PAAs) with distributed control and processing electronics at the surface of an antenna aperture offer numerous advantages for radar communications. Large-area active PAAs on flexible substrates are of particular interest in NASA s space radars due to their efficient inflatable package that can be rolled up during transportation and deployed in space. Such an inflatable package significantly reduces stowage volume and mass. Because of these performance and packaging advantages, large-area inflatable active PAAs are highly desired in NASA s surface-to-orbit and surface-to-relay communications. To address the issues of flexible electronics, a room-temperature printing process of active phased-array antennas on a flexible Kapton substrate was developed. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proved feasible for the PAA system. This innovation is a new type of fully inkjet-printable, two-dimensional, high-frequency PAA on a flexible substrate at room temperature. The designed electronic circuit components, such as the FET switches in the phase shifter, metal interconnection lines, microstrip transmission lines, etc., are all printed using a special inkjet printer. Using the developed technology, entire 1x4, 2x2, and 4x4 PAA systems were developed, packaged, and demonstrated at 5.3 GHz. Several key solutions are addressed in this work to solve the fabrication issues. The source/drain contact is developed using droplets of silver ink printed on the source/drain areas prior to applying CNT thin-film. The wet silver ink droplets allow the silver to wet the CNT thin-film area and enable good contact with the source and drain contact after annealing. A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This film is also used as the media for transferring the aligned CNT thin-film on the device substrate. A simple and cost-effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior to bonding on the first substrate. Inkjet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the bottom layer. It is then annealed to form a good connection. One-dimensional and two-dimensional PAAs were fabricated and characterized. In these circuits, multilayer metal interconnects were used to make a complete PAA system.

Subbaraman, Harish↗

Inrush Current Suppression Circuit and Method for Controlling When a Load May Be Fully Energized

A circuit and method for controlling when a load may be fully energized includes directing electrical current through a current limiting resistor that has a first terminal connected to a source terminal of a field effect transistor (FET), and a second terminal connected to a drain terminal of the FET. The gate voltage magnitude on a gate terminal of the FET is varied, whereby current flow through the FET is increased while current flow through the current limiting resistor is simultaneously decreased. A determination is made as to when the gate voltage magnitude on the gate terminal is equal to or exceeds a predetermined reference voltage magnitude, and the load is enabled to be fully energized when the gate voltage magnitude is equal to or exceeds the predetermined reference voltage magnitude.

Schwerman, Paul↗

Current Source Logic Gate

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Krasowski, Michael J.↗

Cryogenic Parametric Characterization of Gallium Nitride Switches

This report presents the parametric characterization results of four GaN field-effect transistor (FET) devices from three manufacturers, one of which is a cascode device, and compares those results to a Si power metal-oxide-semiconductor fieldeffect transistor (MOSFET) and a SiC power MOSFET. The devices were first characterized at ambient temperature, then at cryogenic temperatures down to -196 C (LN2 temperature), and finally at ambient temperature again in the event that the device parameters were permanently affected by the cryogenic temperatures. In general, the results indicate that the GaN devices show significant improvement overall at cryogenic temperatures in the parameters characterized, such as onresistance and leakage currents, compared to the Si and SiC devices. The results show that the SiC device tested should not be used at cryogenic temperatures due to the significant increase in on-resistance. The results also show that the GaN and Si parameters characterized were either not affected by the cryogenic temperatures or changed by no more than +/-20 percent post LN2 submersion. The device that exhibited the most parametric change post LN2 submersion was the SiC power MOSFET in its leakage currents.

Gonzalez, Marcelo C.↗