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At least 109 records · Page 6

Sensing circuits for multiwire proportional chambers

Integrated sensing circuits were designed, fabricated, and packaged for use in determining the direction and fluence of ionizing radiation passing through a multiwire proportional chamber. CMOS on sapphire was selected because of its high speed and low power capabilities. The design of the proposed circuits is described and the results of computer simulations are presented. The fabrication processes for the CMOS on sapphire sensing circuits and hybrid substrates are outlined. Several design options are described and the cost implications of each discussed. To be most effective, each chip should handle not more than 32 inputs, and should be mounted on its own hybrid substrate.

Peterson, H. T.↗

A 20-GHz IMPATT transmitter

The engineering development of a solid state transmitter amplifier operating in the 20 GHz frequency band. The development effort involved a variety of disciplines including IMPATT device development, circulator design, simple and multiple diode circuits designs, and amplifier integration and test.

Chan, J. L.↗

Radiation Hardening of Computers

Single-event upsets reduced by use of oversize transistors. Computers made less susceptible to ionizing radiation by replacing bipolar integrated circuits with properly designed, complementary metaloxide-semiconductor (CMOS) circuits. CMOS circuit chips made highly resistant to single-event upset (SEU), especially when certain feedback resistors are incorporated. Redesigned chips also consume less power than original chips.

Nichols, D. K.↗

Analog MOS integrated circuits

The goal was to design single-chip lowpass filters with constant group delay in the pass band and 60 dB minimum attenuation in the stop band. The desired 3 dB frequencies are (in Hertz) 2.5, 5, 10, 20, 40, 80, 160, and 320. A filter class that satisfies the constant delay (linear phase) requirement while providing quite a narrow transition band is the Bessel-Chebyshev filters. It was found that the 7th order Bessel-Chebyshev response satisfied the requirement of the filter.

Temes, Gabor C.↗

The design of radiation-hardened ICs for space - A compendium of approaches

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Kerns, Sherra E.↗

W-band monolithic oscillator using InAlAs/InGaAs HEMT

A W-band monolithic integrated oscillator circuit was designed and fabricated using submicron HEMT technology. The oscillation frequency was around 81 GHz and the power was -7 dBm at the chip level. This is the first report of an InAlAs/InGaAs monolithic oscillator operating at the W-band.

Kwon, Y.↗

Analog VLSI neural network integrated circuits

Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

Kub, F. J.↗

Next generation VLSI tools

This paper focuses on what features would be useful in VLSI Computer Aided Design Tools and Systems to be used in the next five to ten years. Examples of current design tasks will be used to emphasize the areas where new or expanded VLSI CAD tools are needed. To provide a basis for projecting the future of VLSI tools, a brief history of the evolution of VLSI design software and hardware platforms is presented. The role of design methodology is considered with respect to the anticipated scale of future VLSI design projects. Future requirements of design verification and manufacturing testing are projected based on the challenge of surviving in a competitive market. Examples of VLSI tools reflect the author's involvement on VLSI design teams developing integrated circuits for disk memory and other computer peripherals for the last eight years.

Gibson, J.↗

A new variable testability measure

In this paper, we propose a new Variable Testability Measure (VTM) for implementing testability at the high-level synthesis stage of the design process of integrated circuits. This new approach, based on binary decision diagrams, representing fully functional blocks of a circuit, and on their cyclomatic testability measures. It manipulates dataflow blocks to predict whether the circuit is testable and the vector set required to test it.

Jamoussi, M.↗

Analysis of microstrip dipoles and slots transversely coupled to a microstrip line using the FDTD method

Printed dipole elements and their complement, linear slots, are elementary radiators that have found use in low-profile antenna arrays. Low-profile antenna arrays, in addition to their small size and low weight characteristics, offer the potential advantage of low-cost, high-volume production with easy integration with active integrated circuit components. The design of such arrays requires that the radiation and impedance characteristics of the radiating elements be known. The FDTD (Finite-Difference Time-Domain) method is a general, straight-forward implementation of Maxwell's equations and offers a relatively simple way of analyzing both printed dipole and slot elements. Investigated in this work is the application of the FDTD method to the analysis of printed dipole and slot elements transversely coupled to an infinite transmission line in a multilayered configuration. Such dipole and slot elements may be used in dipole and slot series-fed-type linear arrays, where element offsets and interelement line lengths are used to obtain the desired amplitude distribution and beam direction, respectively. The design of such arrays is achieved using transmission line theory with equivalent circuit models for the radiating elements. In an equivalent circuit model, the dipole represents a shunt impedance to the transmission line, where the impedance is a function of dipole offset, length, and width. Similarly, the slot represents a series impedance to the transmission line. The FDTD method is applied to single dipole and slot elements transversely coupled to an infinite microstrip line using a fixed rectangular grid with Mur's second order absorbing boundary conditions. Frequency-dependent circuit and scattering parameters are obtained by saving desired time-domain quantities and using the Fourier transform. A Gaussian pulse excitation is applied to the microstrip transmission line, where the resulting reflected signal due to the presence of the radiating element is used to determine the equivalent element impedance.

Tulintseff, A. N.↗

SiC Optically Modulated Field-Effect Transistor

An optically modulated field-effect transistor (OFET) based on a silicon carbide junction field-effect transistor (JFET) is under study as, potentially, a prototype of devices that could be useful for detecting ultraviolet light. The SiC OFET is an experimental device that is one of several devices, including commercial and experimental photodiodes, that were initially evaluated as detectors of ultraviolet light from combustion and that could be incorporated into SiC integrated circuits to be designed to function as combustion sensors. The ultraviolet-detection sensitivity of the photodiodes was found to be less than desired, such that it would be necessary to process their outputs using high-gain amplification circuitry. On the other hand, in principle, the function of the OFET could be characterized as a combination of detection and amplification. In effect, its sensitivity could be considerably greater than that of a photodiode, such that the need for amplification external to the photodetector could be reduced or eliminated. The experimental SiC OFET was made by processes similar to JFET-fabrication processes developed at Glenn Research Center. The gate of the OFET is very long, wide, and thin, relative to the gates of typical prior SiC JFETs. Unlike in prior SiC FETs, the gate is almost completely transparent to near-ultraviolet and visible light. More specifically: The OFET includes a p+ gate layer less than 1/4 m thick, through which photons can be transported efficiently to the p+/p body interface. The gate is relatively long and wide (about 0.5 by 0.5 mm), such that holes generated at the body interface form a depletion layer that modulates the conductivity of the channel between the drain and the source. The exact physical mechanism of modulation of conductivity is a subject of continuing research. It is known that injection of minority charge carriers (in this case, holes) at the interface exerts a strong effect on the channel, resulting in amplification of the photon-detection signal. A family of operating curves characterizing the OFET can be generated in a series of measurements performed at different intensities of incident ultraviolet light.

Tabib-Azar, Massood↗

Low-Noise Amplifier for 100 to 180 GHz

A three-stage monolithic millimeter-wave integrated-circuit (MMIC) amplifier designed to exhibit low noise in operation at frequencies from about 100 to somewhat above 180 GHz has been built and tested. This is a prototype of broadband amplifiers that have potential utility in diverse applications, including measurement of atmospheric temperature and humidity and millimeter-wave imaging for inspecting contents of opaque containers. Figure 1 depicts the amplifier as it appears before packaging. Figure 2 presents data from measurements of the performance of the amplifier as packaged in a WR-05 waveguide and tested in the frequency range from about 150 to about 190 GHz. The amplifier exhibited substantial gain throughout this frequency range. Especially notable is the fact that at 165 GHz, the noise figure was found to be 3.7 dB, and the noise temperature was found to be 370 K: This is less than half the noise temperature of the prior state of the art.

Kangaslahti, Pekka↗

VLSI Design of a Turbo Decoder

A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

Fang, Wai-Chi↗

Progress in integrated-circuit horn antennas for receiver applications. Part 1: Antenna design

The purpose of this work is to present a systematic method for the design of multimode quasi-integrated horn antennas. The design methodology is based on the Gaussian beam approach and the structures are optimized for achieving maximum fundamental Gaussian coupling efficiency. For this purpose, a hybrid technique is employed in which the integrated part of the antennas is treated using full-wave analysis, whereas the machined part is treated using an approximate method. This results in a simple and efficient design process. The developed design procedure has been applied for the design of a 20, a 23, and a 25 dB quasi-integrated horn antennas, all with a Gaussian coupling efficiency exceeding 97 percent. The designed antennas have been tested and characterized using both full-wave analysis and 90 GHz/370 GHz measurements.

Eleftheriades, George V.↗

Design rules for CMOS/SOS circuits

Report presents design rules for advanced-technology integrated circuits made by self-aligned silicongate complementary - metal - oxide - semiconductor/silicon-on-sapphir (CMOS/SOS) process.

Source record↗

Monolithic microwave integrated circuit devices for active array antennas

Two different aspects of active antenna array design were investigated. The transition between monolithic microwave integrated circuits and rectangular waveguides was studied along with crosstalk in multiconductor transmission lines. The boundary value problem associated with a discontinuity in a microstrip line is formulated. This entailed, as a first step, the derivation of the propagating as well as evanescent modes of a microstrip line. The solution is derived to a simple discontinuity problem: change in width of the center strip. As for the multiconductor transmission line problem. A computer algorithm was developed for computing the crosstalk noise from the signal to the sense lines. The computation is based on the assumption that these lines are terminated in passive loads.

Mittra, R.↗

Design and status of the RF-digitizer integrated circuit

An integrated circuit currently under development samples a bandpass-limited signal at a radio frequency in quadrature and then performs a simple sum-and-dump operation in order to filter and lower the rate of the samples. Downconversion to baseband is carried out by the sampling step itself through the aliasing effect of an appropriately selected subharmonic sampling frequency. Two complete RF digitizer circuits with these functions will be implemented with analog and digital elements on one GaAs substrate. An input signal, with a carrier frequency as high as 8 GHz, can be sampled at a rate as high as 600 Msamples/sec for each quadrature component. The initial version of the chip will sign-sample (1-bit) the input RF signal. The chip will contain a synthesizer to generate a sample frequency that is a selectable integer multiple of an input reference frequency. In addition to the usual advantages of compactness and reliability associated with integrated circuits, the single chip will replace several steps required by standard analog downconversion. Furthermore, when a very high initial sample rate is selected, the presampling analog filters can be given very large bandwidths, thereby greatly reducing phase and delay instabilities typically introduced by such filters, as well as phase and delay variation due to Doppler changes.

Rayhrer, B.↗