The effect of phase detector characteristics on phase lock loop design parameters
Effect of phase detector characteristics on phase lock loop design parameters
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Effect of phase detector characteristics on phase lock loop design parameters
Threshold performance of phase locked loop demodulators
Statistical behavior steady state phase error and time to cycle slip for phase lock loops
Digital phase locked loop for FM signals demodulation, considering system nonlinear difference equation
An all digital phase-locked loop (DPLL) is designed, analyzed, and tested. Three specific configurations are considered, generating first, second, and third order DPLL's; and it is found, using a computer simulation of a noise spike, and verified experimentally, that of these configurations the second-order system is optimum from the standpoint of threshold extension. This substantiates results obtained for analog PLL's.
A pulse phase locked loop system according to the present invention is described. A frequency generator such as a voltage controlled oscillator (VCO) generates an output signal and a reference signal having a frequency equal to that of the output signal. A transmitting gate gates the output frequency signal and this gated signal drives a transmitting transducer which transmits an acoustic wave through a material. A sample/hold samples a signal indicative of the transmitted wave which is received by a receiving transducer. Divide-by-n counters control these gating and sampling functions in response to the reference signal of the frequency generator. Specifically, the output signal is gated at a rate of F/h, wherein F is the frequency of the output signal and h is an integer; and the received signal is sampled at a delay of F/n wherein n is an integer.
A pulse phase locked loop system according to the present invention is described. A frequency generator such as a voltage controlled oscillator (VCO) generates an output signal and a reference signal having a frequency equal to that of the output signal. A transmitting gate gates the output frequency signal and this gated signal drives a transmitting transducer which transmits an acoustic wave through a material. A sample/hold samples a signal indicative of the transmitted wave which is received by a receiving transducer. Divide-by-n counters control these gating and sampling functions in response to the reference signal of the frequency generator. Specifically, the output signal is gated at a rate of F/h, wherein F is the frequency of the output signal and h is an integer; and the received signal is sampled at a delay of F/n wherein n is an integer.
Bit-synchronizers utilize all-digital phase-lock loops that are referenced to a high frequency digital clock. Phase-lock loop of first design acquires frequency within nominal range and tracks phase; second design is modified for random binary data by addition of simple transition detector; and third design acquires frequency over wide dynamic range.
A system that couples several phase-locked loops to improve carrier tracking performance is considered. It coherently combines the received carrier signals at geographically separated ground antennas to increase the total effective aperture. The received carrier's phases are automatically aligned to enhance the received carrier signal-to-noise ratio. The system's tracking performance is assessed in terms of rms phase jitter. It is shown that the phase-locked loop in the first receiver, where the carrier arraying is performed, tracks the received carrier phase using the received carrier power from all receivers.
Random walk model for determining cycle slipping in phase locked loops
We report high-resolution frequency study and phase locking have been performed on a terahertz (THz) quantum-cascade vertical-external-cavity surface-emitting laser (QC-VECSEL) operating around 2.5 THz. A subharmonic diode mixer is used to down convert the THz signal to a 100 MHz intermediate frequency that is phase locked to a stable 100 MHz microwave reference. Between 90% and 95% of the QC-VECSEL signal is locked within 2 Hz of the multiplied RF reference, and amplitude fluctuations on the order of 1%–10% are observed, depending on the bias point of the QC-VECSEL. The bandwidth of the locking loop is ~1 MHz. Many noise peaks in the IF signal are observed, likely corresponding to mechanical resonances in the 10 Hz–10 kHz. These peaks are generally -30 to -60 dB below the main tone and are below the phase noise level of the multiplied RF reference that ultimately limits the phase noise of the locked QC-VECSEL.
Detection and measurement of cycle skipping and phase offsets in frequency multiplying phase-lock filters
Phase lock receiver designed for arraying four independently steerable antennas
A phase-locked semiconductor array wherein the lasing regions of the array are spaced an effective distance apart such that the modes of oscillation of the different lasing regions are phase-locked to one another. The center-to-center spacing between the lasing regions is non-uniform. This variation in spacing perturbs the preferred 180.degree. phase difference between adjacent lasing regions thereby providing an increased yield of arrays exhibiting a single-lobed, far-field radiation pattern.
This is Volume I of a two-volume work on the theory, of phase-locked receivers, with pertinent reference material on practical receiver design. Volume I is primarily devoted to the performance of carrier-tracking loops, including a rigorous treatment of narrow-band systems having IF limiters. The bulk of the work is based on a theoretical linear model, but a nonlinear method is also presented to predict behavior near the threshold. The emphasis throughout the work is toward completeness, simplicity, and internal consistency of the material assembled. Part I of this Volume is an exposition of the theory, the resulting equations, and the design philosophy that have enabled the phase-lock concept to evolve into the basic principle underlying the most sensitive receivers il, the world today. Part II is a condensed version of Part I, intended as a quick reference to formulas, definitions, and salient design considerations.
Rate equations analysis of phase-locked semiconductor laser arrays has been carried out. It was found that for given (laser) current densities, the photon density distribution in the array elements is that particular one which maximizes the total photon density. The results of this analysis were then combined with the waveguide properties of the laser array waveguide, yielding a basic model of phase-locked diode laser arrays. This model explains the effects of the variation of the current combination through the array elements on its mode structure that were observed recently.
For advanced digital space transponders, the Digital Phased-Locked Loops (DPLLs) can be designed using the available analog loops. DPLLs considered in this paper are derived from the Analog Phase-Locked Loop (APLL) using S-domain mapping techniques.
Minimization of voltage controlled oscillator noise effects in phase locked loops