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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 109 records · Page 6
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Interaction between Convection and Heat Transfer in Crystal Growth

Crystals are integral components in some of our most sophisticated and rapidly developing industries. Single crystals are solids with the most uniform structures that can be obtained on an atomic scale. Because of their structural uniformity, crystals can transmit acoustic and electromagnetic waves and charged particles with essentially no scattering or interferences. This transparency, which can be selectively modified by controlled additions of impurities known as dopants, is the foundation of modern electronic industry. It has brought about widespread application of crystals in transistors, lasers, microwave devices, infrared detectors, magnetic memory devices, and many other magnets and electro-optic components. The performance of a crystal depends strongly on its compositional homogeneity. For instance, in modern microcircuitry, compositional variations of a few percent (down to a submicron length scale) can seriously jeopardize predicted yields. Since crystals are grown by carefully controlled phase transformations, the compositional adjustment in the solid is often made during growth from the nutrient. Hence, a detailed understanding of mass transfer in the nutrient is essential. Moreover, since mass transfer is often the slowest process during growth, it is usually the rate limiting mechanism. Crystal growth processes are usually classified according to the nature of the parent phase. Nevertheless, whether the growth occurs by solidification from a melt (melt growth), nucleation from a solution (solution growth), condensation from a vapor (physical vapor transport) or chemical reaction of gases (chemical vapor deposition), the parent phase is a fluid. As is with most non-equilibrium processes involving fluids, liquid or vapor, fluid motion plays an important role, affecting both the concentration and temperature gradients at the soli-liquid interface.

Source record↗
NASA NTRS1981

Monolithic CCD-array readout

Circuit is self-biasing, with differential current-to-voltage conversion. CMOS current-differencing readout consists of dc-balanced pair of virtual ground stages and current-differencing circuit similar to circuit mirror. Triode multiplier cell replaces test sources to form monolithic configuration. Transistors belonging to selected multiplier cell need to be duplicated for each multiplier within correlator chip. Remaining elements form part of readout and may be scaled as single common readout stage.

Farnsworth, D. L.↗
DOE OSTI2025

Large scale polymer toughening of two-dimensional materials revealed by in situ TEM fracture tests and multiscale simulations

Two-dimensional (2D) materials offer significant potential for applications in energy-harvesting devices, batteries, sensors, and transistors. However, their intrinsic brittleness makes them prone to mechanical failure, limiting their practical use. In this work, we perform in situ transmission electron microscopy (TEM) fracture tests on monolayer MoSe2 and uncover an extrinsic toughening effect induced by an ultrathin adsorbed polystyrene adlayer. This adlayer substantially enhances the fracture resistance of the 2D flakes. Through a combination of molecular dynamics simulations and finite element analysis, we elucidate the molecular mechanism behind this toughening effect. Further, it arises from the active crack-bridging behavior of entangled polymer chains and the formation of a fracture process zone that stabilizes crack propagation and increases the energy required for crack extension. The proposed toughening mechanism offers a pathway to improving the mechanical reliability of 2D material-based devices by mitigating the risk of sudden failure.

2D materials↗
DOE OSTI2024

Machine learning without a processor: Emergent learning in a nonlinear analog network

Standard deep learning algorithms require differentiating large nonlinear networks, a process that is slow and power-hungry. Electronic contrastive local learning networks (CLLNs) offer potentially fast, efficient, and fault-tolerant hardware for analog machine learning, but existing implementations are linear, severely limiting their capabilities. These systems differ significantly from artificial neural networks as well as the brain, so the feasibility and utility of incorporating nonlinear elements have not been explored. Here, we introduce a nonlinear CLLN—an analog electronic network made of self-adjusting nonlinear resistive elements based on transistors. We demonstrate that the system learns tasks unachievable in linear systems, including XOR (exclusive or) and nonlinear regression, without a computer. We find our decentralized system reduces modes of training error in order (mean, slope, curvature), similar to spectral bias in artificial neural networks. The circuitry is robust to damage, retrainable in seconds, and performs learned tasks in microseconds while dissipating only picojoules of energy across each transistor. This suggests enormous potential for fast, low-power computing in edge systems like sensors, robotic controllers, and medical devices, as well as manufacturability at scale for performing and studying emergent learning.

Science & Technology - Other Topics↗
NASA NTRS1998

Genetically Engineered Nanostructure Devices

Material variations on an atomic scale enable the quantum mechanical functionality of devices such as resonant tunneling diodes (RTDs), quantum well infrared photodetectors (QWIPs), quantum well lasers, and heterostructure field effect transistors (HFETs).

NEMO↗
DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗
NASA NTRS2003

Nanotubes May Break Through "Chip Wall"

In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.

Laufenberg, Larry↗
NASA NTRS1995

Nanoelectronics: Opportunities for future space applications

Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.

Frazier, Gary↗
DOE OSTI2023

Imaging Field–Driven Melting of a Molecular Solid at the Atomic Scale

Solid–liquid phase transitions are basic physical processes, but atomically resolved microscopy has yet to capture their full dynamics. A new technique is developed for controlling the melting and freezing of self–assembled molecular structures on a graphene field–effect transistor (FET) that allows phase–transition behavior to be imaged using atomically resolved scanning tunneling microscopy. This is achieved by applying electric fields to 2,3,5,6–tetrafluoro–7,7,8,8–tetracyanoquinodimethane–decorated FETs to induce reversible transitions between molecular solid and liquid phases at the FET surface. Nonequilibrium melting dynamics are visualized by rapidly heating the graphene substrate with an electrical current and imaging the resulting evolution toward new 2D equilibrium states. An analytical model is developed that explains observed mixed–state phases based on spectroscopic measurement of solid and liquid molecular energy levels. The observed nonequilibrium melting dynamics are consistent with Monte Carlo simulations.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Toward High-Throughput Deposition of III-V Materials and Devices Using Halide Vapor Phase Epitaxy: Preprint

III-V devices are used in countless applications due to their excellent physical properties. They could become more prevalent, especially in area-intensive applications such as solar power, if they can achieve significant cost decreases through increasing scale. The development of high-throughput growth systems can help to achieve this scale, leading to the use of III-V devices in areas where they are not currently economically feasible. Here, we describe a pilot production, pseudo inline HVPE reactor with the potential to greatly increase the throughput of III-V devices. We show computational modeling results that both informed system design and the understanding of the impact of different process parameters on the deposition. We show the throughput possibilities of this reactor with an example solar cell device design but note that this system is agnostic to the device structure and can be used to increase the throughput of lasers, LEDs, transistors, and more III-V devices.

high throughput↗
DOE OSTI2021

Intrinsic synaptic plasticity of ferroelectric field effect transistors for online learning

Nanoelectronic devices emulating neuro-synaptic functionalities through their intrinsic physics at low operating energies is imperative toward the realization of brain-like neuromorphic computers. In this work, we leverage the non-linear voltage dependent partial polarization switching of a ferroelectric field effect transistor to mimic plasticity characteristics of biological synapses. Here, we provide experimental measurements of the synaptic characteristics for a 28nm high-k metal gate technology based device and develop an experimentally calibrated device model for large-scale system performance prediction. Decoupled read-write paths, ultra-low programming energies and the possibility of arranging such devices in a cross-point architecture demonstrate the synaptic efficacy of the device. Our hardware-algorithm co-design analysis reveals that the intrinsic plasticity of the ferroelectric devices has potential to enable unsupervised local learning in edge devices with limited training data

42 ENGINEERING↗
NASA NTRS2002

High-Temperature Electronics: A Role for Wide Bandgap Semiconductors?

It is increasingly recognized that semiconductor based electronics that can function at ambient temperatures higher than 150 C without external cooling could greatly benefit a variety of important applications, especially-in the automotive, aerospace, and energy production industries. The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300 C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog very large scale integrated circuits in this temperature range. However, practical operation of silicon power devices at ambient temperatures above 200 C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once the technology for realizing these devices become sufficiently developed that they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

Neudeck, Philip G.↗
NASA NTRS2007

Using G4FETs as a Data Router for In-Plane Crossing of Signal Paths

Theoretical analysis and some experiments have demonstrated that siliconon- insulator (SOI) 4-gate transistors the type known as G(exp 4)FETs could be efficiently used for in-plane crossing of signal paths. Much of the effort of designing very-large-scale integrated (VLSI) circuits is focused on area-efficient routing of signals. The main source of difficulty in VLSI signal routing is the requirement to prevent crossing, in the same plane, of wires that are meant to be kept electrically insulated from each other. Consequently, it often becomes necessary to design and build VLSI circuits in multiple layers with vias (connections between conductors in different layers at selected locations). Suitable devices that would prevent, or at least sufficiently suppress, undesired electrical coupling (cross-talk) between wires crossing in the same plane would enable compact, simpler implementation complex interconnection networks with in-plane crossings that, heretofore, have not been possible in VLSI circuitry. The use of G4FETs as in-plane signal-crossing devices or routers, in combination with the use of G(exp 4)FETs as universal programmable logic gates, would create opportunities for reducing complexity in VLSI design.

Fijany, Amir↗
DOE OSTI2020

Accessing Atomic-scale Phosphorus Dopant Distribution in Precise Silicon Devices by Advanced STEM Imaging and Spectroscopy

The structural and chemical characterization at the atomic-scale plays a critical role in understanding the structure-property relationship in precise electrical devices such as those produced by atomic-precision advanced manufacturing (APAM). APAM, utilizing hydrogen lithography in a scanning tunneling microscope, offers a potential pathway to ultra-efficient transistors, and has been developed to produce phosphorus (P)-based donor devices integrated into bare Si substrates. Structural characterization of the buried, Si with P dopant (Si:P) delta-layer in the devices by scanning transmission electron microscopy (STEM), however, is a challenge due to similar atomic number and low concentration of the P dopants. In this paper, we describe several efforts of utilizing advanced STEM imagining and spectroscopic techniques to quantify the Si:P deltalayers. STEM imaging combining low-angle and high-angle annular dark-field (LAADF, HAADF) detectors as well as atomic-scale elemental mapping using energy-dispersive X-ray spectroscopy (EDS) are used to reveal the P and defect distribution across the delta-layer processed under various thermal conditions.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Manipulating high-temperature superconductivity by oxygen doping in Bi2Sr2CaCu2O8+δ thin flakes

Abstract Harnessing the fascinating properties of correlated oxides requires precise control of their carrier density. Compared to other methods, oxygen doping provides an effective and more direct way to tune the electronic properties of correlated oxides. Although several approaches, such as thermal annealing and oxygen migration, have been introduced to change the oxygen content, a continuous and reversible solution that can be integrated with modern electronic technology is much in demand. Here, we report a novel ionic field-effect transistor using solid Gd-doped CeO2 as the gate dielectric, which shows a remarkable carrier-density-tuning ability via electric-field-controlled oxygen concentration at room temperature. In Bi2Sr2CaCu2O8+δ (Bi-2212) thin flakes, we achieve a reversible superconductor–insulator transition by driving oxygen ions in and out of the samples with electric fields, and map out the phase diagram all the way from the insulating regime to the over-doped superconducting regime by continuously changing the oxygen doping level. Scaling analysis indicates that the reversible superconductor–insulator transition for the Bi-2212 thin flakes follows the theoretical description of a two-dimensional quantum phase transition. Our work provides a route for realizing electric-field control of phase transition in correlated oxides. Moreover, the configuration of this type of transistor makes heterostructure/interface engineering possible, thus having the potential to serve as the next-generation all-solid-state field-effect transistor.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2024

Investigating the Effects of Individual Neutron-Induced Defects in Bipolar Junction Transistors

Here, this study investigates neutron-induced displacement damage in Bipolar Junction Transistors (BJTs) using TCAD models informed by Deep-Level-Transient-Spectroscopy (DLTS) data. These models are calibrated and validated against experimental measurements performed at various neutron fluences. Both npn and pnp transistor configurations are studied to analyze the effects of individual traps on carrier recombination and base leakage currents. In npn transistors, deep traps (0.42 eV from the conduction band) dominate at low voltages, while shallow traps (0.17 eV from the conduction band) become prominent at higher voltages. Conversely, pnp transistors have base leakage current predominantly due to deep-level traps. The study observes a notable trend in trap density versus fluence, characterized by a linear relationship on a log-log scale. These insights into defect evolution under radiation conditions are crucial for optimizing semiconductor device reliability and performance in radiation-prone environments.

42 ENGINEERING↗
DOE OSTI2020

Au-free low-temperature ohmic contacts for AlGaN/AlN/GaN heterostructures

We report Au-free, Ti/Al/Ta ohmic contact on the AlGaN/AlN/GaN heterostructure using low annealing temperature is studied in this paper. With SiCl 4 plasma treatment at the recess-etched contact region, a low contact resistance of 0.52 Ω mm and a low sheet resistance of 373 Ω/sq are achieved after annealing at 550 °C for 30 s. The low annealing temperature also leads to better surface morphology. Furthermore, AlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) are fabricated with the 550 °C, 30 s annealed Ti/Al/Ta ohmic contacts, and a maximum transconductance of 123 mS/mm and a maximum drain current of 510 mA/mm are obtained for a gate length of 4 μm. Based on Silvaco's Atlas device simulation framework, a scaled-down device with a short gate length of 1 μm would produce a maximum drain current density of 815 mA/mm. It indicates that the direct current performance of the HEMTs with the ohmic metal proposed in this work is considerably better than that with Au-based ohmic contact.

42 ENGINEERING↗