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Conceptual transistor embedded in photovoltaic diode promises to increase efficiency to more than 20 percent. Solar-cell transistor has front-surface contact, rear contact, and floating emitter. Variety of other contact and junction configurations possible, but do not offer ease of fabrication in combination with high performance.
A programmable, automated transistor test system was built to supply experimental data on new and advanced power semiconductors. The data will be used for analytical models and by engineers in designing space and aircraft electric power systems. A pulsed power technique was used at low duty cycles in a nondestructive test to examine the dynamic switching characteristic curves of power transistors in the 500 to 1000 V, 10 to 100 A range. Data collection, manipulation, storage, and output are operator interactive but are guided and controlled by the system software.
This report describes the low-temperature transistor modules designed for use with the MSFC mid-infrared array. The modules were developed in the Space Science Laboratory at Marshall Space Flight Center with Center Director's Discretionary Funds. The transistors (JFETs), which operate at a temperature of 77 K, are epoxied to a copper surface attached to a Teflon substrate. The module substrate insulates the JFETs from the 1.5K detector work surfaces and provides a convenient mounting structure for additional components such as solder pins. These modules have maintained their structural integrity during repeated temperature cycling, and they have to be convenient during maintenance and servicing of the infrared array.
The D60T, D62T, and D75T transistors in the nuclear reactor were irradiated with bias voltage and high current I sub c vs. V sub ec curves were obtained to evaluate gain degradation at high power levels. Pre- and post-irradiation high current switching tests were performed to evaluate the response. The gamma ray damage work done at Sandia was correlated with the neutron work done at the O.S.U. reactor with the above specified transistors. Theoretical analyses of damage and electrical performance were conducted in terms of semiconductor physics. The experimental high current pulser was improved in order to measure switching time changes which are less than one microsecond at currents of 100 to 200 amperes for in-situ testing.
Equivalent base resistance added. Theoretical study develops equations for parameters of Gummel-Poon model of bipolar junction transistor: includes saturation current, amplification factors, charging times, knee currents, capacitances, and resistances. Portion of study concerned with base region goes beyond Gummel-Poon analysis to provide more complete understanding of transistor behavior. Extended theory useful in simulation of single-event upset (SEU) caused in logic circuits by cosmic rays or other ionizing radiation.
The use of nuclear reactors to generate electrical power for future space missions will require the electrical components used in the power conditioning, control, and transmission subsystem to operate in the associated radiation environments. An initial assessment of neutron irradiation on the electrical and switching characteristics of commercial high power NPN bipolar transistors was investigated. The results clearly show the detrimental effects caused by neutron irradiation on the electrical and switching characteristics of the NPN bipolar power transistor.
Quarter-micrometer gate-length high-electron-mobility transistors (HEMTs) for cryogenic low-noise application with very low light sensitivity have been developed. At room temperature, these exhibit a noise figure of 0.4 dB with associated gain of 15 dB at 8 GHz. At a temperature of 12.5 K the minimum noise temperature of 5.3 +/- 1.5 K has been measured at 8.5 GHz, which is the best noise performance observed to date for any microwave transistors. The results clearly demonstrate the potential for low-temperature low-noise applications.
A novel contact regrowth technique for the formation of extremely low nonalloyed ohmic contacts is reported. The successful demonstration of this technique is reported on an InGaAs/InAlAs hot-electron transistor device. For the investigated InGaAs-based structure, the regrown contacting scheme reported includes an In(0.53)Ga(0.47)As layer, an InAs/GaAs strained-layer superlattice, and an InAs cap, all heavily doped n type with Si. A very low specific contact resistance of 1.8 x 10 to the -7th ohm sq cm to the base layer is obtained. The higher current densities achieved in the transistor characteristics are in close agreement with calculations, and a contact model is presented explaining the poor results of conventional nonalloyed contacts.
Porous-floating-gate, "vertical" field-effect transistor proposed as programmable analog memory device especially suitable for use in electronic neural networks. Analog value of electrical conductance of device represents synaptic weight (strength of synaptic connection) repeatedly modified by application of suitable writing or erasing voltage. Suited for hardware implementations of massively parallel neural-network architectures for two important reasons: vertical transistor structure requires only two external electrodes, and use of tailored amorphous semiconductors provides choice of very wide range of low conductivity values, dictated by overall power dissipation requirements in massively parallel neural-network circuits.
Simple configuration for wiring of multiple parallel-connected switching transistors minimizes stray wiring inductance while providing for use of balancing transformers, which equalize currents in transistors. Currents balanced on twisted pairs of wires. Because twisted pairs carry both "hot-side" and return currents, this configuration has relatively low inductance.
Electrodes of a high power, microwave field effect transistor are substantially matched to external input and output networks. The field effect transistor includes a metal ground plane layer, a dielectric layer on the ground plane layer, a gallium arsenide active region on the dielectric layer, and substantially coplanar spaced source, gate, and drain electrodes having active segments covering the active region. The active segment of the gate electrode is located between edges of the active segments of the source and drain electrodes. The gate and drain electrodes include inactive pads remote from the active segments. The pads are connected directly to the input and output networks. The source electrode is connected to the ground plane layer. The space between the electrodes and the geometry of the electrodes extablish parasitic shunt capacitances and series inductances that provide substantial matches between the input network and the gate electrode and between the output network and the drain electrode. Many of the devices are connected in parallel and share a common active region, so that each pair of adjacent devices shares the same source electrodes and each pair of adjacent devices shares the same drain electrodes. The gate electrodes for the parallel devices are formed by a continuous stripe that extends between adjacent devices and is connected at different points to the common gate pad.
High-gain AlxGa1-xAs/GaAs npn double heterojunction bipolar transistors developed for use as phototransistors in optoelectronic integrated circuits, especially in artificial neural networks. Transistors perform both photodetection and saturating-amplification functions of neurons. Good candidates for such application because structurally compatible with laser diodes and light-emitting diodes, detect light, and provide high current gain needed to compensate for losses in holographic optical elements.
Further development efforts yield alternative version of transistors described in "High-Gain AlxGa1-xAs/GaAs Transistors For Neural Networks" (NPO-18101). Efforts focused on determining effects of various aspects of design and of fabrication processes upon leakage currents and on current gain.
Transistor design for extremely high frequency applications requires consideration of the interaction between the device and the circuit to which it is connected. Traditional analytical transistor models are to approximate at some of these frequencies and may not account for variations of dopants and semiconductor materials (especially some of the newer materials) within the device. Physically based models of device performance are required. These are based on coupled systems of partial differential equations and typically require 20 minutes of Cray computer time for a single AC operating point. A technique is presented to extract parameters from a few partial differential equation solutions for the device to create a nonlinear equivalent circuit model which runs in approximately 1 second of personal computer time. This nonlinear equivalent circuit model accurately replicates the contact current properties of the device as computed by the partial differential solver on which it is based. Using the nonlinear equivalent circuit model of the device, optimization of systems design can be performed based on device/circuit interactions.
A simple straight-forward Karnaugh map logic design procedure for realization of multiple-valued logic circuits is presented in this paper. Pass transistor logic gates are used to realize multiple-valued networks. This work is an extension of pass transistor implementations for binary-valued logic.
Hardware description languages such as VHDL have evolved to aid in the design of systems with large numbers of elements and a wide range of electronic and logical abstractions. For high performance circuits, behavioral models may not be able to efficiently include enough detail to give designers confidence in a simulation's accuracy. One option is to provide a link between the VHDL environment and a transistor level simulation environment. The coupling of the Vantage Analysis Systems VHDL simulator and the NOVA simulator provides the combination of VHDL modeling and transistor modeling.
Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.
Heterojunction Bipolar Transistor (HBT) technology has emerged as one of the most promising technologies for ultrahigh-speed integrated circuits. HBT circuits for digital and analog applications, data conversion, and power amplification have been realized, with speed performance well above 20 GHz. At Rockwell, a baseline AlGaAs/GaAs HBT technology has been established in a manufacturing facility. This paper describes the HBT technology, transistor characteristics, and HBT circuits for data acquisition and communication.