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NASA NTRS2012

Nanoengineered Thermal Materials Based on Carbon Nanotube Array Composites

State-of-the-art integrated circuits (ICs) for microprocessors routinely dissipate power densities on the order of 50 W/cm2. This large power is due to the localized heating of ICs operating at high frequencies and must be managed for future high-frequency microelectronic applications. As the size of components and devices for ICs and other appliances becomes smaller, it becomes more difficult to provide heat dissipation and transport for such components and devices. A thermal conductor for a macro-sized thermal conductor is generally inadequate for use with a microsized component or device, in part due to scaling problems. A method has been developed for providing for thermal conduction using an array of carbon nanotubes (CNTs). An array of vertically oriented CNTs is grown on a substrate having high thermal conductivity, and interstitial regions between adjacent CNTs in the array are partly or wholly filled with a filler material having a high thermal conductivity so that at least one end of each CNT is exposed. The exposed end of each CNT is pressed against a surface of an object from which heat is to be removed. The CNT-filler-composite adjacent to the substrate provides improved mechanical strength to anchor CNTs in place, and also serves as a heat spreader to improve diffusion of heat flux from the smaller volume (CNTs) to a larger heat sink.

Li, Jun↗

NASA NTRS2012

Dynamically Reconfigurable Systolic Array Accelerator

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

Dasu, Aravind↗

NASA NTRS2013

Hyperspectral Microwave Atmospheric Sounder (HyMAS) Architecture and Design Accommodations

The Hyperspectral Microwave Atmospheric Sounder (HyMAS) is being developed at Lincoln Laboratories and accommodated by the Goddard Space Flight Center for a flight opportunity on a NASA research aircraft. The term "hyperspectral microwave" is used to indicate an all-weather sounding that performs equivalent to hyperspectral infrared sounders in clear air with vertical resolution of approximately 1 km. Deploying the HyMAS equipped scanhead with the existing Conical Scanning Microwave Imaging Radiometer (CoSMIR) shortens the path to a flight demonstration. Hyperspectral microwave is achieved through the use of independent RF antennas that sample the volume of the Earth s atmosphere through various levels of frequencies, thereby producing a set of dense, spaced vertical weighting functions. The simulations proposed for HyMAS 118/183-GHz system should yield surface precipitation rate and water path retrievals for small hail, soft hail, or snow pellets, snow, rainwater, etc. with accuracies comparable to those of the Advanced Technology Microwave Sounder. Further improvements in retrieval methodology (for example, polarization exploitation) are expected. The CoSMIR instrument is a packaging concept re-used on HyMAS to ease the integration features of the scanhead. The HyMAS scanhead will include an ultra-compact Intermediate Frequency Processor (IFP) module that is mounted inside the door to improve thermal management. The IFP is fabricated with materials made of Low-Temperature Co-fired Ceramic (LTCC) technology integrated with detectors, amplifiers, A/D conversion and data aggregation. The IFP will put out 52 channels of 16 bit data comprised of 4-9 channel data streams for temperature profiles and 2-8 channel streams for water vapor. With the limited volume of the existing CoSMIR scanhead and new HyMAS front end components, the HyMAS team at Goddard began preliminary layout work inside the new drum. Importing and re-using models of the shell, the scan head computer, and the slip rings developed for CoSMIR was the starting point. The next step was to modify the antenna faceplate to accommodate the dimensions of the three dual polarization Gaussian Optics Antenna (GOA) assemblies. Two mechanical concepts for the core technology, the hyperspectral IFP, were captured in a design tradeoff. Connector models considered minimum bend radii for the IFP analog connectors. Hyperspectral imaging is accomplished by strategically using a short wavelength intermediate frequency of 18-29 GHz, and thus reducing the size of components in the connection of the front end to the IFP. The SMK (2.92mm) Series connector will lay near the hinge line to minimize its flexing. The digital output of the IFP will use a Serial Peripheral Interface (SPI) that must be accommodated by the scan head computer. To make that computer more reliable, maintainable, and forward compatible with the 52 HyMAS channels, a testbed of the scan head, calibration, and archive computers and the PIC24 microprocessor that resides on the IFP is in development. The computers will be programmed using a new framework application called Interoperable Remote Component (IRC). This software allows flexibility to program computers that communicate with each other and can adapt easily to the emerging HyMAS requirements for data format, algorithms, and graphical user interface (GUI). It is expected that the CoSMIR instrument will cut over to the IRC after it is adapted on an updated CoSMIR testbed.

Hilliard, Lawrence↗

NASA NTRS2013

Silicon Heat Pipe Array

Improved methods of heat dissipation are required for modern, high-power density electronic systems. As increased functionality is progressively compacted into decreasing volumes, this need will be exacerbated. High-performance chip power is predicted to increase monotonically and rapidly with time. Systems utilizing these chips are currently reliant upon decades of old cooling technology. Heat pipes offer a solution to this problem. Heat pipes are passive, self-contained, two-phase heat dissipation devices. Heat conducted into the device through a wick structure converts the working fluid into a vapor, which then releases the heat via condensation after being transported away from the heat source. Heat pipes have high thermal conductivities, are inexpensive, and have been utilized in previous space missions. However, the cylindrical geometry of commercial heat pipes is a poor fit to the planar geometries of microelectronic assemblies, the copper that commercial heat pipes are typically constructed of is a poor CTE (coefficient of thermal expansion) match to the semiconductor die utilized in these assemblies, and the functionality and reliability of heat pipes in general is strongly dependent on the orientation of the assembly with respect to the gravity vector. What is needed is a planar, semiconductor-based heat pipe array that can be used for cooling of generic MCM (multichip module) assemblies that can also function in all orientations. Such a structure would not only have applications in the cooling of space electronics, but would have commercial applications as well (e.g. cooling of microprocessors and high-power laser diodes). This technology is an improvement over existing heat pipe designs due to the finer porosity of the wick, which enhances capillary pumping pressure, resulting in greater effective thermal conductivity and performance in any orientation with respect to the gravity vector. In addition, it is constructed of silicon, and thus is better suited for the cooling of semiconductor devices.

Yee, Karl Y.↗

NASA NTRS2012

Reliability of High I/O High Density CCGA Interconnect Electronic Packages under Extreme Thermal Environment

This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions. Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages such as high interconnect density, very good thermal and electrical performances, compatibility with standard surface-mount packaging assembly processes, and so on. CCGA packages are used in space applications such as in logic and microprocessor functions, telecommunications, payload electronics, and flight avionics. As these packages tend to have less solder joint strain relief than leaded packages or more strain relief over lead-less chip carrier packages, the reliability of CCGA packages is very important for short-term and long-term deep space missions. We have employed high density CCGA 1152 and 1272 daisy chained electronic packages in this preliminary reliability study. Each package is divided into several daisy-chained sections. The physical dimensions of CCGA1152 package is 35 mm x 35 mm with a 34 x 34 array of columns with a 1 mm pitch. The dimension of the CCGA1272 package is 37.5 mm x 37.5 mm with a 36 x 36 array with a 1 mm pitch. The columns are made up of 80% Pb/20%Sn material. CCGA interconnect electronic package printed wiring polyimide boards have been assembled and inspected using non-destructive x-ray imaging techniques. The assembled CCGA boards were subjected to extreme temperature thermal atmospheric cycling to assess their reliability for future deep space missions. The resistance of daisy-chained interconnect sections were monitored continuously during thermal cycling. This paper provides the experimental test results of advanced CCGA packages tested in extreme temperature thermal environments. Standard optical inspection and x-ray non-destructive inspection tools were used to assess the reliability of high density CCGA packages for deep space extreme temperature missions. Keywords: Extreme temperatures, High density CCGA qualification, CCGA reliability, solder joint failures, optical inspection, and x-ray inspection.

high density CCGA qualifications↗

NASA NTRS2010

Use of a Frequency Divider to Evaluate an SOI NAND Gate Device, Type CHT-7400, for Wide Temperature Applications

Frequency dividers constitute essential elements in designing phase-locked loop circuits and microwave systems. In addition, they are used in providing required clocking signals to microprocessors and can be utilized as digital counters. In some applications, particularly space missions, electronics are often exposed to extreme temperature conditions. Therefore, it is required that circuits designed for such applications incorporate electronic parts and devices that can tolerate and operate efficiently in harsh temperature environments. While present electronic circuits employ COTS (commercial-off- the-shelf) parts that necessitate and are supported with some form of thermal control systems to maintain adequate temperature for proper operation, it is highly desirable and beneficial if the thermal conditioning elements are eliminated. Amongst these benefits are: simpler system design, reduced weight and size, improved reliability, simpler maintenance, and reduced cost. Devices based on silicon-on-insulator (SOI) technology, which utilizes the addition of an insulation layer in the device structure to reduce leakage currents and to minimize parasitic junctions, are well suited for high temperatures due to reduced internal heating as compared to the conventional silicon devices, and less power consumption. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a divide-by-two frequency divider circuit built using COTS SOI logic gates was evaluated over a wide temperature range and thermal cycling to determine suitability for use in space exploration missions and terrestrial fields under extreme temperature conditions.

Patterson, Richard L.↗

NASA NTRS2013

Reliability of CCGA 1152 and CCGA 1272 Interconnect Packages for Extreme Thermal Environments

Ceramic column grid array (CCGA) packages have been increasing in use based on their advantages of high interconnect density, very good thermal and electrical performance, and compatibility with standard surface-mount packaging assembly processes. CCGA packages are used in space applications such as in logics and microprocessor functions, telecommunications, flight avionics, and payload electronics. As these packages tend to have less solder joint strain relief than leaded packages, the reliability of CCGA packages is very important for short- and long-term space missions. Certain planetary satellites require operations of thermally uncontrolled hardware under extremely cold and hot temperatures with large diurnal temperature change from day to night. The planetary protection requires the hardware to be baked at +125 C for 72 hours to kill microbugs to avoid any biological contamination, especially for sample return missions. Therefore, the present CCGA package reliability research study has encompassed the temperature range of 185 to +125 C to cover various NASA deep space missions. Advanced 1152 and 1272 CCGA packaging interconnects technology test hardware objects have been subjected to ex treme temperature thermal cycles from 185 to +125 C. X-ray inspections of CCGA packages have been made before thermal cycling. No anomalous behavior and process problems were observed in the x-ray images. The change in resistance of the daisy-chained CCGA interconnects was measured as a function of increasing number of thermal cycles. Electrical continuity measurements of daisy chains have shown no anomalies, even until 596 thermal cycles. Optical inspections of hardware have shown a significant fatigue for CCGA 1152 packages over CCGA 1272 packages. No catastrophic failures have been observed yet in the results. Process qualification and assembly are required to optimize the CCGA assembly processes. Optical inspections of CCGA boards have been made after 258 and 596 thermal cycles. Corner columns have started showing significant fatigue per optical inspection results.

Ramesham, Rajeshuni↗

NASA NTRS2013

Miga Aero Actuator and 2D Machined Mechanical Binary Latch

Shape memory alloy (SMA) actuators provide the highest force-to-weight ratio of any known actuator. They can be designed for a wide variety of form factors from flat, thin packages, to form-matching packages for existing actuators. SMA actuators can be operated many thousands of times, so that ground testing is possible. Actuation speed can be accurately controlled from milliseconds to position and hold, and even electronic velocity-profile control is possible. SMA actuators provide a high degree of operational flexibility, and are truly smart actuators capable of being accurately controlled by onboard microprocessors across a wide range of voltages. The Miga Aero actuator is a SMA actuator designed specifically for spaceflight applications. Providing 13 mm of stroke with either 20- or 40-N output force in two different models, the Aero actuator is made from low-outgassing PEEK (polyether ether ketone) plastic, stainless steel, and nickel-titanium SMA wires. The modular actuator weighs less than 28 grams. The dorsal output attachment allows the Aero to be used in either PUSH or PULL modes by inverting the mounting orientation. The SPA1 actuator utilizes commercially available SMA actuator wire to provide 3/8-in. (approx. =.1 cm) of stroke at a force of over 28 lb (approx. = .125 N). The force is provided by a unique packaging of the single SMA wire that provides the output force of four SMA wires mechanically in parallel. The output load is shared by allowing the SMA wire to slip around the output attachment end to adjust or balance the load, preventing any individual wire segment from experiencing high loads during actuation. A built-in end limit switch prevents overheating of the SMA element following actuation when used in conjunction with the Miga Analog Driver [a simple MOSFET (metal oxide semiconductor field-effect transistor) switching circuit]. A simple 2D machined mechanical binary latch has been developed to complement the capabilities of SMA wire actuators. SMA actuators typically perform ideally as latch-release devices, wherein a spring-loaded device is released when the SMA actuator actuates in one direction. But many applications require cycling between two latched states open and closed.

Gummin, Mark A.↗

NASA NTRSDate not supplied

Delay Tolerant, Radio Frequency Identification (RFID )-enabled Sensing

Radio Frequency Identification (RFID) technology offers a completely passive method to transmit fixed data sequences from an RFID tag, which typically doesn’t have its own power supply, to an interrogator. Radio frequency (RF) energy harvested from the interrogator is rectified by the tag and used to charge an integrated circuit (IC). The IC then modulates the received signal with the data stored on the tag and reflects the energy back to the interrogator. RFID has seen great proliferation in terrestrial inventory management applications, and it has recently made the jump to spaceflight applications onboard the International Space Station, augmenting an existing optical bar‐code infrastructure for tracking supplies. A number of advanced automated logistics management (ALM) concepts employing RFID are currently being developed and evaluated, including so‐called “smart” shelves, cubbies, and trash receptacles using low‐power, embeddable RFID interrogators. An infrastructure where both crew members and robotic assistants, such as autonomous free flyers, are similarly equipped with small RFID interrogators seems likely. It therefore behooves us to consider extending this infrastructure beyond ALM to applications such as low power, embedded sensing. Typically, data on an RFID tag can only be written by an RFID interrogator, using interrogator energy. In recent years, however, a few efforts have focused on using that energy to drive data acquisition from the tag IC, allowing the tag to modify its stored data sequence with sensor data before replying to an interrogator. In this way, the tag can act as a completely passive sensing device. One problem exists with this approach, however: the tag cannot gather data when an interrogator is not present. Thus, strictly passive RFID sensing tags cannot gather data at regular intervals, in the manner of a typical wireless sensor network, without careful, and impractical, planning of mobile interrogator movements. To address this shortcoming, we look to a recent advance in RFID technology which allows an external microprocessor to power the tag IC and write directly into its RFID memory using a wired serial interface. In this paradigm, data gathering is driven by a small, on‐board power supply (using batteries or harvested energy), and data transfer is provided passively through the RFID interrogation service. Since communication typically consumes the lion’s share of power in WSNs, such a technique has the potential to enable extremely long‐lived, embedded wireless sensing when used with extremely low‐current microcontrollers. Since the communication channel is only open when an interrogator is present and actively interrogating the RFID sensing tag, transport of periodically‐sampled sensor data presents itself as a delay/disruption‐tolerant networking (DTN) problem. In this paper, we present the design of a DTN‐like overlay on the common EPC Global, Class 1, Generation 2 RFID standard. This overlay allows seamless, guaranteed data transfer using the EPC Global protocol, supporting extremely low‐power, embedded sensing using an infrastructure likely to be already in place for ALM applications. We evaluate a prototype implementation of a complete end‐to‐end system using a robotic RFID interrogation agent, and we present future directions for the development of this sensing technique.

Raymond S. Wagner↗

NASA NTRS2014

The Roots of Beowulf

The first Beowulf Linux commodity cluster was constructed at NASA's Goddard Space Flight Center in 1994 and its origins are a part of the folklore of high-end computing. In fact, the conditions within Goddard that brought the idea into being were shaped by rich historical roots, strategic pressures brought on by the ramp up of the Federal High-Performance Computing and Communications Program, growth of the open software movement, microprocessor performance trends, and the vision of key technologists. This multifaceted story is told here for the first time from the point of view of NASA project management.

Beowulf↗

NASA NTRS2014

Dynamically Reconfigurable Systolic Array Accelorators

A polymorphic systolic array framework that works in conjunction with an embedded microprocessor on an FPGA, that allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms and extendable to more complex applications in the area of aerospace embedded systems.

Dasu, Aravind↗

NASA NTRS2015

2nd Generation QUATARA Flight Computer Project

Single core flight computer boards have been designed, developed, and tested (DD&T) to be flown in small satellites for the last few years. In this project, a prototype flight computer will be designed as a distributed multi-core system containing four microprocessors running code in parallel. This flight computer will be capable of performing multiple computationally intensive tasks such as processing digital and/or analog data, controlling actuator systems, managing cameras, operating robotic manipulators and transmitting/receiving from/to a ground station. In addition, this flight computer will be designed to be fault tolerant by creating both a robust physical hardware connection and by using a software voting scheme to determine the processor's performance. This voting scheme will leverage on the work done for the Space Launch System (SLS) flight software. The prototype flight computer will be constructed with Commercial Off-The-Shelf (COTS) components which are estimated to survive for two years in a low-Earth orbit.

Falker, Jay↗

NASA NTRS1996

High Angular Sensitivity, Absolute Rotary Encoding Device with Polygonal Mirror and Stand-Alone Diffraction Gratings

A device for position encoding of a rotating shaft in which a polygonal mirror having a number of facets is mounted to the shaft and a monochromatic light beam is directed towards the facets. The facets of the polygonal mirror direct the light beam to a stand-alone low line density diffraction grating to diffract the monochromatic light beam into a number of diffracted light beams such that a number of light spots are created on a linear array detector. An analog-to-digital converter is connected to the linear array detector for reading the position of the spots on the linear array detector means. A microprocessor with memory is connected to the analog-to-digital converter to hold and manipulate the data provided by the analog-to-digital converter on the position of the spots and to compute the position of the shaft based upon the data from the analog-lo-digital converter.

Leviton, Douglas B.↗

NASA NTRS2016

Photonic Integrated Circuits

Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

Laser↗

NASA NTRS2015

Reconfigurable Very Long Instruction Word (VLIW) Processor

Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

Velev, Miroslav N.↗

NASA NTRS2016

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally approx.300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

data acquisition↗

NASA NTRS2015

Human Research Program Advanced Exercise Concepts (AEC) Overview

Exercise countermeasures provide benefits that are crucial for successful human spaceflight, to mitigate the spaceflight physiological deconditioning which occurs during exposure to microgravity. The NASA Human Research Program (HRP) within the Human Exploration and Operations Mission Directorate (HEOMD) is managing next generation Advanced Exercise Concepts (AEC) requirements development and candidate technology maturation to Technology Readiness Level (TRL) 7 (ground prototyping and flight demonstration) for all exploration mission profiles from Multi Purpose Crew Vehicle (MPCV) Exploration Missions (up to 21 day duration) to Mars Transit (up to 1000 day duration) missions. These validated and optimized exercise countermeasures systems will be provided to the ISS Program and MPCV Program for subsequent flight development and operations. The International Space Station (ISS) currently has three major pieces of operational exercise countermeasures hardware: the Advanced Resistive Exercise Device (ARED), the second-generation (T2) treadmill, and the cycle ergometer with vibration isolation system (CEVIS). This suite of exercise countermeasures hardware serves as a benchmark and is a vast improvement over previous generations of countermeasures hardware, providing both aerobic and resistive exercise for the crew. However, vehicle and resource constraints for future exploration missions beyond low Earth orbit will require that the exercise countermeasures hardware mass, volume, and power be minimized, while preserving the current ISS capabilities or even enhancing these exercise capabilities directed at mission specific physiological functional performance and medical standards requirements. Further, mission-specific considerations such as preservation of sensorimotor function, autonomous and adaptable operation, integration with medical data systems, rehabilitation, and in-flight monitoring and feedback are being developed for integration with the exercise countermeasures systems. Numerous technologies have been considered and evaluated against HRP-approved functional device requirements for these extreme mission profiles, and include wearable sensors, exoskeletons, flywheel, pneumatic, and closed-loop microprocessor controlled motor driven systems. Each technology has unique advantages and disadvantages. The Advanced Exercise Concepts project oversees development of candidate next generation exercise countermeasures hardware, performs trade studies of current and state of the art exercise technologies, manages and supports candidate systems physiological evaluations with human test subjects on the ground, in flight analogs and flight. The near term goal is evaluation of candidate systems in flight, culminating in an integrated candidate next generation exercise countermeasures suite on the ISS which coalesces research findings from HRP disciplines in the areas of exercise performance for muscle, bone, cardiovascular, sensorimotor, behavioral health, and nutrition for optimal benefit to the crew.

Countermeasures↗

NASA NTRS2016

Photonic Integrated Circuits

laser↗