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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Design and Construction of the CMS Outer Tracker for the Phase-2 Upgrade

The High Luminosity LHC (HL-LHC) is expected to deliver an integrated luminosity of 3000-4000~fb$^{-1}$ after 10 years of operation with peak instantaneous luminosity reaching about 5-7.5$\times10^{34}$cm$^{-2}$s$^{-1}$. During Long Shutdown 3, several components of the CMS detector will undergo major changes, called Phase-2 upgrades, to be able to operate in the challenging environment of the HL-LHC. The current CMS tracker will be replaced. The Phase-2 Outer Tracker (OT) will have high radiation tolerance, higher granularity, and the capability to handle higher data rates. Moreover, the OT will provide tracking information to the Level-1 trigger, for the first time at hadron colliders, allowing trigger rates to be kept at a sustainable level without sacrificing physics potential. For this, the OT will be made of modules with two closely spaced silicon sensors read out by front-end ASICs, which can correlate hits in the two sensors creating short track segments (stubs), used for tracking in the L1 track finder. The modules come in two flavors: strip-strip (2S) and pixel-strip (PS), containing different sensor configurations and multiple ASICs. This contribution will present the design of the Phase-2 OT, the first results with pre-production devices, and the quality assurance procedures used to ensure the functionality of the modules: from fulfilling the precision specification of the module assembly procedure to ensuring the proper communication among the module's ASICs.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

Test and characterization of finely segmented pixel CZT detectors for future hard x-ray missions

The NuSTAR (Nuclear Spectroscopic Telescope Array) mission was launched in 2012, and it has successfully deployed the first orbiting telescopes to focus high energy X-ray (3 - 79 keV) light, providing a wealth of new information on high-energy X-rays sources. Follow-up missions, such as the proposed HEX-P, BEST, and FORCE, could perform a deeper black hole census providing a more refined measurement of black hole spins, allowing for greater knowledge about supermassive black holes. Here, these missions are motivated by the recent breakthroughs in the hard X-ray mirror technologies, where mirrors, either made of monolithic silicon segments, or made directly or via replication of shells, demonstrate the feasibility of making hard X-ray mirrors with angular resolutions of 5-10 arc-seconds Half Power Diameter (HPD) compared to the NuSTAR’s 1 arc-minute HPD. Such a high angular resolution requires matched detectors with higher degree of segmentation to fully benefit from the achievable improved spatial resolution. In the above framework, the HEXID ASIC, a novel pixelated front-end suitable for reading out a finely segmented CZT sensor with 150 μm pixel pitch in a hexagonal arrangement has been developed. This readout pixelated chip is capable of processing photon-generated charge packets over a large dynamic range (from 2 keV up to 180 keV), while keeping a low input noise (ENC <20 e - ). In this work, the initial characterization of the ASIC prototype will be presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Final Report DE-SC0020773

The DOE/NNSA sought development of innovative portable neutron/x-ray cameras for imaging and, when coupled with a portable source, also for radiography. This project focused on developing such a device that promises to have excellent resolution, while also providing neutron/gamma separation. We developed an Application Specific Integrated Circuit (ASIC) to be employed in conjunction with existing sensor technologies and modern assembly techniques. The concepts developed were a combination of new novel techniques and an innovative implementation of existing methods boosted by technological advances in ASIC performance.

61 RADIATION PROTECTION AND DOSIMETRY↗
DOE OSTI2022

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail. The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ~36mV/ke - when configured in High Gain Mode, and ~20mV/ke - when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ~68e - rms and ~80e - rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ~ 200ps time bin and the chip can deal with a maximum flux of ~ 3.6MHzmm –2 s –1 . In photon counting mode, the chip can deal with up to ~ 5GHzmm –2 s –1 . The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Ultrafast radiographic imaging and tracking: An overview of instruments, methods, data, and applications

Ultrafast radiographic imaging and tracking (U-RadIT) use state-of-the-art ionizing particle and light sources to experimentally study sub-nanosecond transients or dynamic processes in physics, chemistry, biology, geology, materials science and other fields. These processes are fundamental to modern technologies and applications, such as nuclear fusion energy, advanced manufacturing, communication, and green transportation, which often involve one mole or more atoms and elementary particles, and thus are challenging to compute by using the first principles of quantum physics or other forward models. One of the central problems in U-RadIT is to optimize information yield through, e.g. high-luminosity X-ray and particle sources, efficient imaging and tracking detectors, novel methods to collect data, and large-bandwidth online and offline data processing, regulated by the underlying physics, statistics, and computing power. We review and highlight recent progress in: (a.) Detectors such as high-speed complementary metal-oxide semiconductor (CMOS) cameras, hybrid pixelated array detectors integrated with Timepix4 and other application-specific integrated circuits (ASICs), and digital photon detectors; (b.) U-RadIT modalities such as dynamic phase contrast imaging, dynamic diffractive imaging, and four-dimensional (4D) particle tracking; (c.) U-RadIT data and algorithms such as neural networks and machine learning, and (d.) Applications in ultrafast dynamic material science using XFELs, synchrotrons and laser-driven sources. Hardware-centric approaches to U-RadIT optimization are constrained by detector material properties, low signal-to-noise ratio, high cost and long development cycles of critical hardware components such as ASICs. Interpretation of experimental data, including comparisons with forward models, is frequently hindered by sparse measurements, model and measurement uncertainties, and noise. Alternatively, U-RadIT make increasing use of data science and machine learning algorithms, including experimental implementations of compressed sensing. Machine learning and artificial intelligence approaches, refined by physics and materials information, may also contribute significantly to data interpretation, uncertainty quantification and U-RadIT optimization.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

The STAR Forward Silicon Tracker

The Forward Silicon Tracker (FST) is a pivotal component of the forward upgrade of the Solenoidal Tracker at RHIC (STAR), designed to discern hadron charge signs with a momentum resolution better than 30% for 0.2 < p T < 2GeV/c in the 2.5 < η < 4 pseudorapidity range. Its compact design features three disks along the beam direction, minimized material budget, and scattering effects. The FST uses Hamamatsu’s p-in-n silicon strip sensors with a double metal layer that enables efficient signal routing to the readout electronics, enhancing overall detector performance. The flexible hybrid boards, essential for the readout system, are constructed with Kapton and copper layers to optimize signal handling and power distribution. These boards connect silicon strips to analogue pipeline ASIC APV25-S1 chips, which read up to 128 channels each. A cooling system with nonconducting, volatile NOVEC 7200 coolant at 22.2 °C mitigates ASIC-generated heat. Furthermore, the FST enhances forward tracking performance at STAR as an integral part of the forward upgrade.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2021

Production and tests of the ADDC for the Micromegas detector of the ATLAS New Small Wheel

The Large Hadron Collider (LHC) at CERN will perform a series of upgrades to allow luminosity increases during the next physics runs expected from 2022 on. These will also significantly increase the trigger rates of all the detectors. As part of the ATLAS Phase-I upgrade, the current Small Wheel muon detectors will be replaced with state-of-the-art New Small Wheel (NSW) detectors to cope with the increased luminosity of the LHC. The Address in Real Time Data Driver Card (ADDC) is designed to transmit the trigger data from the resistive Micro-Mesh Gaseous Structure (Micromegas) detectors of the NSW. The ART ASIC on the ADDC is a customdesigned chip to receive theAddress in Real Time (ART) signals from theVMMfront-end ASIC and perform hit-selection processing. The processed trigger data is then sent to the Trigger Processor (TP) through optical links. A total of 512 ADDCs will be installed on the detector close to the front-end boards. Therefore, those cards must be able to work properly in a high radiation and magnetic field environment. Furthermore, after four rounds of prototyping, the ADDC production was launched in January of 2019. 600 ADDC boards have been produced and tested with an automated test stand. This test setup can simulate the front-end signals and provide "Level-1 Data Driver Card" (L1DDC) functions as well as part of the TP functions. Thus, the ADDC functionality and stability can be verified without the remaining NSW electronics. This paper describes the ADDC hardware prototype development, radiation and integration testing, and the ADDC automated production test procedure.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

Waveform processing using neural network algorithms on the front-end electronics

In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by extracting peak amplitudes, area under pulse envelopes from the raw data, and starting times of signals or time of arrivals. However, such quantities can be estimated using machine learning algorithms on the front-end Application-Specific Integrated Circuits (ASICs), often termed as “edge computing”. Edge computation offers enormous benefits, especially when the analytical forms are not fully known or the registered waveform suffers from noise and imperfections of practical implementations. In this work, we aim to predict peak amplitude from a single waveform snippet whose rising and falling edges containing only 3 to 4 samples. We thoroughly studied two well-accepted neural network algorithms, Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) by varying their model sizes. Further, to better fit front-end electronics, neural network model reduction techniques, such as network pruning methods and variable-bit quantization approaches, were also studied. By combining pruning and quantization, our best performing model has the size of 1.5 KB, reduced from 16.6 KB of its full model counterpart. It can reach mean absolute error of 0.034 comparing to that of a naive baseline of 0.135. Such parameter-efficient and predictive neural network models established feasibility and practicality of their deployment on front-end ASICs.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Electronics for the far-forward CMS muon detector upgrade, ME0

Abstract With the High Luminosity upgrade of the Large Hadron Collider (LHC) we expect increased instantaneous luminosities up to 7.5 × 10 34 cm −2 s −1 , or five times more than the original values. In order to maintain performance of the Compact Muon Solenoid (CMS) experiment under these conditions, ME0 is one of three new muon sub-detectors being added, along with GE1/1 and GE2/1, which use the triple Gas Electron Multiplier (GEM) technology. ME0 is designed to cover the forward region of 2.0 < | η | < 2.8, thus improving muon reconstruction at high background rates by supplementing other overlapping muon subsystems up to | η | = 2.4, while also extending the acceptance for the first time to | η | = 2.8. The readout electronics for ME0 must be designed to accommodate high data rates and be sufficiently radiation hard to operate close to the beamline. The Optohybrid (OH) board for ME0, which reads out data from the front-end VFAT3b ASICs, has therefore been designed to operate without an FPGA (unlike GE1/1 and GE2/1) to ensure radiation hardness. The ME0 OH uses the radiation-hard CERN-designed lpGBT ASIC and VTRx+ optical transceiver module for high bandwidth optical links up to 10.24 Gb/s. The backend system is based on the ATCA standard. The design and development status of the readout electronics for ME0 is presented, along with recent results from integration tests performed using the first prototypes.

Instruments & Instrumentation↗
DOE OSTI2024

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Finally, further development of the eFPGA technology and its application to collider detector readout is discussed.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Beam test performance studies of CMS Phase-2 Outer Tracker module prototypes

A new tracking detector will be installed as part of thePhase-2 upgrade of the CMS detector for the high-luminosity LHC era.This tracking detector includes the Inner Tracker, equipped withsilicon pixel sensor modules, and the Outer Tracker, consisting ofmodules with two parallel stacked silicon sensors. The Outer Trackerfront-end ASICs will be able to correlate hits from chargedparticles in these two sensors to perform on-module discriminationof transverse momenta (p$_{T}$). The p$_{T}$information is generated at a frequency of 40 MHz and will be usedin the Level-1 trigger decision of CMS. Prototypes of theso-called 2S modules were tested at the Test Beam Facility at DESYHamburg between 2019 and 2020. These modules use the finalfront-end ASIC, the CMS Binary Chip (CBC), and for the firsttime the Concentrator Integrated Circuit (CIC), optical readoutand on-module power conversion. In total, seven modules were tested,one of which was assembled with sensors irradiated with protons. Animportant aspect was to show that it is possible to read out modulessynchronously. A cluster hit efficiency of about 99.75 % wasachieved for all modules. The CBC p$_{T}$ discriminationmechanism has been verified to work together with the CIC andoptical readout. The measured module performance meets therequirements for operation in the upgraded CMS tracking detector.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Lifetime study of the ColdADC for the Deep Underground Neutrino Experiment

ColdADC is a custom ASIC digitizer implemented in 65 nm CMOS technology using specialized techniques for long-term reliability in cryogenic environments. ColdADC was developed for use in the DUNE Far Detector complex, which will consist of four liquid argon time projection chambers. Each contains 17 kilotons liquid argon as the target material in order to measure neutrino oscillations. Approximately 40,000 ColdADC ASICs will be installed for DUNE in the first two large detectors and will be operated at cryogenic temperatures during the experiment without replacement. The lifetime of the ColdADC is a critical parameter affecting the data quality and physics sensitivity of the experiment. A measurement of the lifetime of the ColdADC was carried out, and the results shown in this paper assure orders of magnitude longer lifetime of the ColdADC than the planned operation time of the detectors.

Front-end electronics for detector readout↗
DOE OSTI2025

High-energy X-ray imaging with a Germanium MM-PAD hybrid pixel detector

Germanium is a high-Z sensor material with excellent energy resolution and attractive properties for high-energy photon detection. Despite its advantages, the need for cryogenic operation and challenges in the fabrication of pixelated high-purity germanium have hindered the development of segmented detectors. We report on the fabrication and performance of a germanium imaging detector with 150 μm pixel pitch hybridized to the MM-PAD ASIC. The detector was capable of high-resolution radiographic imaging and has a fast temporal response. Additionally, we describe the detector's upper operating temperature limits using both the MM-PAD and MARS ASICs, achieving stable operation up to 130 K and 190 K, respectively.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Characterizing electron-collecting CdTe for use in a 77 ns burst-rate imager

The Keck-PAD (pixel array detector) was developed at Cornell as a burst-rate imager capable of recording images from successive electron bunches (153 ns period) from the Advanced Photon Source (APS). Both Si and hole-collecting Schottky CdTe have been successfully bonded to this ASIC (application-specific integrated circuit) and used with this frame rate. The facility upgrades at the APS will lower the bunch period to 77 ns, which will require modifications to the Keck-PAD electronics to image properly at this reduced period. In addition, operation at high X-ray energies will require a different sensor material having a shorter charge collection time. For the target energy of 40 keV for this project, simulations have shown that electron-collecting CdTe should allow >90% charge collection within 35 ns. This collection time will be sufficient to sample the signal from one frame and prepare for the next. 750 µm-thick electron-collecting Schottky CdTe has been obtained from Acrorad and bonded to two different charge-integrating ASICs developed at Cornell, the Keck-PAD and the CU-APS-PAD. Carrier mobility has been investigated using the detector response to single X-ray bunches at the Cornell High Energy Synchrotron Source and to a pulsed optical laser. The tests indicate that the collection time will meet the requirements for 77 ns imaging.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Mixed gain detector configurations for time-resolved X-ray solution scattering

X-ray detection at X-ray free-electron lasers is challenging in part due to the XFEL's extremely short and intense X-ray pulses. Experimental measurements are further complicated by the large fluctuations inherent to the self-amplified spontaneous emission process producing the X-rays. At the Linac Coherent Light Source the ePix10ka2M detector offers multiple gain modes, and auto-ranging between these, to increase the dynamic range while retaining low noise. For diffuse scattering techniques, such as time-resolved X-ray solution scattering, where the shape of the scattering pattern largely does not change between exposures, a fixed mix of different gain modes offers many of the same advantages as auto-ranging. We find that configuring individual ASICs in separate gain modes does not impact the intensity linearity of the gain response and has a limited effect on the effective dynamic range in regions with different gain mode settings while avoiding the complexities of auto-ranging. Small (<5%) non-linear gain contributions arise when pixels on the same ASIC are configured in different gain modes. We present a configuration scheme that is designed to select the optimal mixed gain configuration to minimize effects of saturation in the high-/medium-gain region, while maximizing the number of pixels with higher gain to improve the signal-to-noise ratio.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis

Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

A 3D Implementation of Convolutional Neural Network for Fast Inference

Low latency inference has many applications in edge machine learning. In this paper, we present a run-time configurable convolutional neural network (CNN) inference ASIC design for low-latency edge machine learning. By implementing a 5-stage pipelined CNN inference model in a 3D ASIC technology, we demonstrate that the model distributed on two dies utilizing face-to-face (F2F) 3D integration achieves superior performance. Our experimental results show that the design based on 3D integration achieves 43% better energy-delay product when compared to the traditional 2D technology.

Miniskar, Narasinga Rao↗
DOE OSTI2022

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

97 MATHEMATICS AND COMPUTING↗