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Low-power devices susceptible to cosmic-ray particles. Five MSI device technologies, including TTL, low power TTL, Schottky, CMOS, and low-power Schottky, subjected to 120-MeV krypton-ion beam from cyclotron and monitored for single-event upset. Results find terrestrial application for radiation hardening of electronic devices and systems.
The Space Technology 5 (ST5) mission is a NASA New Millennium Program project that will validate new technologies for future space science missions and demonstrate the feasibility of building launching and operating multiple, miniature spacecraft that can collect research-quality in-situ science measurements. The three satellites in the ST5 constellation will be launched into a sun-synchronous Earth orbit in early 2006. ST5 fits into the 25-kilogram and 24-watt class of very small but fully capable spacecraft. The new technologies and design concepts for a compact power and command and data handling (C&DH) avionics system are presented. The 2-card ST5 avionics design incorporates new technology components while being tightly constrained in mass, power and volume. In order to hold down the mass and volume, and quali& new technologies for fUture use in space, high efficiency triple-junction solar cells and a lithium-ion battery were baselined into the power system design. The flight computer is co-located with the power system electronics in an integral spacecraft structural enclosure called the card cage assembly. The flight computer has a full set of uplink, downlink and solid-state recording capabilities, and it implements a new CMOS Ultra-Low Power Radiation Tolerant logic technology. There were a number of challenges imposed by the ST5 mission. Specifically, designing a micro-sat class spacecraft demanded that minimizing mass, volume and power dissipation would drive the overall design. The result is a very streamlined approach, while striving to maintain a high level of capability, The mission's radiation requirements, along with the low voltage DC power distribution, limited the selection of analog parts that can operate within these constraints. The challenge of qualifying new technology components for the space environment within a short development schedule was another hurdle. The mission requirements also demanded magnetic cleanliness in order to reduce the effect of stray (spacecraft-generated) magnetic fields on the science-grade magnetometer.
Space-based gamma-ray telescopes such as the Fermi Large Area Telescope have used single sided silicon strip detectors to measure the position of incident gamma-rays with high resolution. At lower energies, two dimensional position information within a single detector is required. This talk investigates the use of monolithic CMOS active pixel silicon sensors –AstroPix – as a novel technology for use in future gamma-ray telescopes. Based upon detectors designed for use in the ATLAS detector at the LHC, AstroPix has the potential to maintain the high energy and angular resolution required of a medium-energy gamma-ray telescope while reducing noise with the dual detection and readout capabilities of a CMOS chip. The status of AstroPix development and testing, as well as outlook for application in future telescopes such as the proposed medium-energy gamma-ray telescope AMEGO-X, will be presented.
A CMOS imaging sensor is described that uses active pixel sensor (APS) technology which permits the integration of the detector array with on-chip timing, control and signal chain electronics. This sensor has been used to implement a CMOS APS camera-on-a-chip.
Previous analytical models were extended to predict cosmic ray-induced soft error rates in static MOS memory devices. The effect is due to ionization and can be introduced by high energy, heavy ion components of the galactic environment. The results indicate that the sensitivity of memory cells is directly related to the density of the particular MOS technology which determines the node capacitance values. Hence, CMOS is less sensitive than e.g., PMOS. In addition, static MOS memory cells are less sensitive than dynamic ones due to differences in the mechanisms of storing bits. The flip-flop of a static cell is inherently stable against cosmic ray-induced bit flips. Predicted error rates on a CMOS RAM and a PMOS shift register are in general agreement with previous spacecraft flight data.
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.
The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.
A new class of asynchronous sequential circuits is introduced in this paper. The new design procedures are oriented towards producing asynchronous sequential circuits that are implemented with CMOS VLSI and take advantage of pass transistor technology. The first design algorithm utilizes a standard Single Transition Time (STT) state assignment. The second method introduces a new class of self synchronizing asynchronous circuits which eliminates the need for critical race free state assignments. These circuits arbitrate the transition path action by forcing the circuit to sequence through proper unstable states. These methods result in near minimum hardware since only the transition paths associated with state variable changes need to be implemented with pass transistor networks.
NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.
Advanced Technology Laboratories has designed, built, and tested the first CMOS general-purpose computer. The computer executes 32 instructions that are operation-code compatible with the IBM 360 and RCA Spectra 70 series of computers. The computer is supported by 2k words of main-memory LSI storage and a TTY peripheral for input and output operations. Additionally, a simulator, an assembler, and a loader have been constructed to provide software support to the hardware. This paper provides an overall picture of this computer project.
Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.
As part of NASA's New Millennium Program, the Space Technology 5 mission will validate a variety of technologies for nano-satellite and constellation mission applications. Included are: a miniaturized and low power X-band transponder, a constellation communication and navigation transceiver, a cold gas micro-thruster, two different variable emittance (thermal) controllers, flex cables for solar array power collection, autonomous groundbased constellation management tools, and a new CMOS ultra low-power, radiation-tolerant, +0.5 volt logic technology. The ST-5 focus is on small and low-power. A single-processor, multi-function flight computer will implement direct digital and analog interfaces to all of the other spacecraft subsystems and components. There will not be a distributed data system that uses a standardized serial bus such as MIL-STD-1553 or MIL-STD-1773. The flight software running on the single processor will be responsible for all real-time processing associated with: guidance, navigation and control, command and data handling (C&DH) including uplink/downlink, power switching and battery charge management, science data analysis and storage, intra-constellation communications, and housekeeping data collection and logging. As a nanosatellite trail-blazer for future constellations of up to 100 separate space vehicles, ST-5 will demonstrate a compact (single board), low power (5.5 watts) solution to the data acquisition, control, communications, processing and storage requirements that have traditionally required an entire network of separate circuit boards and/or avionics boxes. In addition to the New Millennium technologies, other major spacecraft subsystems include the power system electronics, a lithium-ion battery, triple-junction solar cell arrays, a science-grade magnetometer, a miniature spinning sun sensor, and a propulsion system.
A survey is presented of NASA-developed technologies and systems that were reaching commercial application in the course of 1999. Attention is given to the contributions of each major NASA Research Center. Representative 'spinoff' technologies include the predictive AI engine monitoring system EMPAS, the GPS-based Wide Area Augmentation System for aircraft navigation, a CMOS-Active Pixel Sensor camera-on-a-chip, a marine spectroradiometer, portable fuel cells, hyperspectral camera technology, and a rapid-prototyping process for ceramic components.
New space missions will increasingly rely on more advanced technologies because of system requirements for higher performance, particularly in instruments and high-speed processing. Component-level reliability challenges with scaled CMOS in spacecraft systems from a bottom-up perspective have been presented. Fundamental Front-end and Back-end processing reliability issues with more aggressively scaled parts have been discussed. Effective thermal management from system-level to the componentlevel (top-down) is a key element in overall design of reliable systems. Thermal management in space systems must consider a wide range of issues, including thermal loading of many different components, and frequent temperature cycling of some systems. Both perspectives (top-down and bottom-up) play a large role in robust, reliable spacecraft system design.
Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.
Dark current degradation, origins, and annealing behavior after x-ray irradiation are studied in a P-type, hole collecting, backside-illuminated image sensor currently being developed at STMicroelectronics and based on deep-trenched photo-MOS pixels. Different biasing conditions during irradiation, i.e. grounded or biased and sequenced, are compared. The dark current increase with total ionizing dose (TID) and the dark current annealing behavior seem to be driven by the backside interface between the P-epitaxy of the pixels and the ONO stack. Despite still being under development, this pixel architecture already exhibits both very good electro-optical performance and a better radiation hardness than pinned photodiode-based CMOS Image sensors that benefit from the same advanced CIS processing technologies. At high total dose range, the photogate challenges custom Radiation-Hardened-by-Design photodiodes by exhibiting a comparable radiation tolerance while bringing new features such as high-resolution or Correlated Double Sampling.
We report low-energy proton and alpha particle SEE data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) that demonstrates the criticality of understanding and using low-energy protons for SEE testing of highly-scaled technologies
Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.