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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1983

FET commutated current-FED inverter

A shunt switch comprised of a field-effect transistor (Q.sub.1) is employed to commutate a current-fed inverter (10) using thyristors (SCR1, SCR2) or bijunction transistors (Q.sub.2, Q.sub.3) in a full bridge (1, 2, 3, 4) or half bridge (5, 6) and transformer (T.sub.1) configuration. In the case of thyristors, a tapped inverter (12) is employed to couple the inverter to a dc source to back bias the thyristors during commutation. Alternatively, a commutation power supply (20) may be employed for that purpse. Diodes (D.sub.1, D.sub.2) in series with some voltage dropping element (resistor R.sub.12 or resistors R.sub.1, R.sub.2 or Zener diodes D.sub.4, D.sub.5) are connected in parallel with the thyristors in the half bridge and transformer configuration to assure sharing the back bias voltage. A clamp circuit comprised of a winding (18) negatively coupled to the inductor and a diode (D.sub.3) return stored energy from the inductor to the power supply for efficient operation with buck or boost mode.

Rippel, Wally E.↗
NASA NTRS2013

Effects of Thermal Cycling on Control and Irradiated EPC 2nd Generation GaN FETs

The power systems for use in NASA space missions must work reliably under harsh conditions including radiation, thermal cycling, and exposure to extreme temperatures. Gallium nitride semiconductors show great promise, but information pertaining to their performance is scarce. Gallium nitride N-channel enhancement-mode field effect transistors made by EPC Corporation in a 2nd generation of manufacturing were exposed to radiation followed by long-term thermal cycling in order to address their reliability for use in space missions. Results of the experimental work are presented and discussed.

field effect transistor↗
NASA NTRS2021

Single-Event Effect Testing of the ON Semiconductor BSS123 N-Channel Logic Level Enhancement Mode FET and the Vishay Si1013R P-Channel MOSFET

This study was undertaken to determine the single event effect (SEE) susceptibility of two different MOSFET components. Heavy-ion testing was conducted at the Lawrence Berkeley National Laboratory (LBNL) Berkeley Accelerator Space Effects (BASE) Facility 88” Cyclotron. Its purpose was to evaluate these devices as candidates for use on Goddard Modular SmallSat Architecture (GMSA) adapter board for the GTOSat project.

Michael J Campola↗
DOE OSTI2021

Effects of polymer grain boundary passivation on organic–inorganic hybrid perovskite field-effect transistors

Despite successful applications of solution-processed organic–inorganic hybrid perovskites (OIHPs) such as archetypical methylammonium lead iodide (MAPI) in high-performance optoelectronic devices including solar cells and light emitting diodes, their application in field-effect transistors (FETs) remains relatively limited due to the unresolved issues caused by ion migration in OIHPs, such as screening of gate electric fields, lowered device on-off ratios and field-effect mobility, and large hysteresis in the FET transfer characteristics. Here, we report improved performances of the MAPI-based FET via a polymer-additive-based grain boundary (GB) passivation approach that suppresses the ion migration. Polycaprolactone (PCL) was incorporated into the MAPI FET as a GB-passivation additive as confirmed by scanning electron and atomic force microscopies. Unlike the typical n-type behavior and large transfer hysteresis in the starting, pristine MAPI FETs, the GB passivation by PCL led to a drastically reduced hysteresis in FET transfer characteristics, while hinting at an ambipolar transport and slight improvement in mobility, indicating a reduced ion migration in the PCL-incorporated MAPI FET. The effect of PCL GB passivation in suppressing ion migration was directly confirmed by the measured, increased activation energy for ion migration in the PCL-incorporated MAPI. Here, the results not only represent the first report of the polymer-additive-based mitigation of the ion migration in the MAPI FET but also suggest potential utilities of the approach for enabling high-performance OIHP FETs and electronic devices in general.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS2010

Fully Printed High-Frequency Phased-Array Antenna on Flexible Substrate

To address the issues of flexible electronics needed for surface-to-surface, surface-to-orbit, and back-to-Earth communications necessary for manned exploration of the Moon, Mars, and beyond, a room-temperature printing process has been developed to create active, phased-array antennas (PAAs) on a flexible Kapton substrate. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proven feasible for phased-array antenna systems. The carrier mobility of an individual CNT is estimated to be at least 100,000 sq cm/V(dot)s. The CNT network in solution has carrier mobility as high as 46,770 sq cm/V(dot)s, and has a large current-density carrying capacity of approx. 1,000 mA/sq cm , which corresponds to a high carrying power of over 2,000 mW/ sq cm. Such high carrier mobility, and large current carrying capacity, allows the achievement of high-speed (>100 GHz), high-power, flexible electronic circuits that can be monolithically integrated on NASA s active phasedarray antennas for various applications, such as pressurized rovers, pressurized habitats, and spacesuits, as well as for locating beacon towers for lunar surface navigation, which will likely be performed at S-band and attached to a mobile astronaut. A fully printed 2-bit 2-element phasedarray antenna (PAA) working at 5.6 GHz, incorporating the CNT FETs as phase shifters, is demonstrated. The PAA is printed out at room temperature on 100-mm thick Kapton substrate. Four CNT FETs are printed together with microstrip time delay lines to function as a 2-bit phase shifter. The FET switch exhibits a switching speed of 0.2 ns, and works well for a 5.6-GHz RF signal. The operating frequency is measured to be 5.6 GHz, versus the state-of-the-art flexible FET operating frequency of 52 MHz. The source-drain current density is measured to be over 1,000 mA/sq cm, while the conventional organic FETs, and single carbon nanotube-based FETs, are typically in the mA to mA/sq cm range. The switching voltage used is 1.8 V, while the state-of-the-art flexible FET has a gate voltage around 50 V. The gate voltage can effectively control the source-drain current with an ON-OFF ratio of over 1,000 obtained at a low Vds bias of 1.8 V. The azimuth steering angles of PAA are measured at 0deg, -14.5deg, -30deg, and 48.6deg. The measured far-field patterns agree well with simulation results. The efficiency of the 2-bit 2-element PAA is measured to be 39 percent, including the loss of transmission line, FET switch, and coupling loss of RF probes. With further optimization, the efficiency is expected to be around 50-60 percent.

Chen, Yihong↗
NASA NTRS2002

Process for a High Efficiency Class D Microwave Power Amplifier Operating in the S-Band

A process and product providing a High Efficiency Microwave Power Amplifier (HEMPA) which propagates S-Band microwave frequency square waves; utilizing a program simulating FETs at high DC-to-RF efficiencies, which analyses linear elements of selected FETs in a frequency domain, and non-linear elements of the FETs in a time domain, and converts the time domain values into the frequency domain, and performs DC and S-parameter simulated measurements based on predefined data for each FET. Individual FET parameters are extracted and isolated by converting the S-parameters to admittance or impedance parameters to derive FET models for each FET, which the program uses to provide a final output of a HEMPA circuit based on iterative simulations of an amplification circuit utilizing microwave topology and frequencies. Iterative simulations of the amplification circuit analyze output values of a plurality of cascaded stages of the FETs, which are arranged in a push-pull configuration.

William Herbert Sims, III↗
NASA NTRS2009

Efficient Multiplexer FPGA Block Structures Based on G4FETs

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Vatan, Farrokh↗
NASA NTRS1990

High-speed dynamic domino circuit implemented with gaas mesfets

A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.

Yang, Long↗
DOE OSTI2025

Working with Bezier Curves as bases for Functional Expansion Tallies

Functional expansion tallies (FETs) are a powerful tool for getting more information per history from Monte Carlo simulations, but in the past they have been constrained to orthogonal bases. Bezier curves, from computer aided design (CAD), could be well suited for FET due to their ability to assume many arbitrary shapes, but are non-orthogonal. Recent development has made non-orthongal FET possible. The convergence of B ´ezier curve FETs in both polynomial order and number of samples is explored. These bases are well suited for representing normal distributions, and opens the door to possible other CAD derived FET bases.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Working with Bézier Curves as bases for Functional Expansion Tallies

Functional expansion tallies (FETs) are powerful tools for getting more information per history from Monte Carlo simulations, but in the past they have been constrained to orthogonal bases. Bézier curves are used widely in computer aided design (CAD) geometry kernels and could be well-suited for FETs due to their ability to assume many arbitrary shapes, but they use nonorthogonal bases. Recent developments in 2021 have made nonorthogonal FETs possible. The convergence of Bézier curve FETs in both polynomial order and number of samples is explored in this work. It is shown that these bases are well-suited for representing normal distributions and this opens the door to the possibility of other CAD-derived FET bases.

97 - MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Fully Inkjet‐Printed, 2D Materials‐Based Field‐Effect Transistor for Water Sensing

Abstract Despite significant progress in solution‐processing of 2D materials, it remains challenging to reliably print high‐performance semiconducting channels that can be efficiently modulated in a field‐effect transistor (FET). Herein, electrochemically exfoliated MoS 2 nanosheets are inkjet‐printed into ultrathin semiconducting channels, resulting in high on/off current ratios up to 10 3 . The reported printing strategy is reliable and general for thin film channel fabrication even in the presence of the ubiquitous coffee‐ring effect. Statistical modeling analysis on the printed pattern profiles suggests that a spaced parallel printing approach can overcome the coffee‐ring effect during inkjet printing, resulting in uniform 2D flake percolation networks. The uniformity of the printed features allows the MoS 2 channel to be hundreds of micrometers long, which easily accommodates the typical inkjet printing resolution of tens of micrometers, thereby enabling fully printed FETs. As a proof of concept, FET water sensors are demonstrated using printed MoS 2 as the FET channel, and printed graphene as the electrodes and the sensing area. After functionalization of the sensing area, the printed water sensor shows a selective response to Pb 2+ in water down to 2 ppb. This work paves the way for additive nanomanufacturing of FET‐based sensors and related devices using 2D nanomaterials.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Commensuration Effects in Layered Nanoparticle Solids.

We have developed a hierarchical nanoparticle transport simulator (HINTS) and adapted it to study commensuration effects in two classes of nanoparticle (NP) solids: (1) a bilayer NP solid (BNS) with an energy offset and (2) a BNS as part of a field effect transistor (FET). HINTS integrates the ab initio characterization of single NPs with the phonon-assisted tunneling transition model of the NP-NP transitions into a kinetic Monte Carlo based simulation of the charge transport in NP solids. First, we studied a BNS with an interlayer energy offset Delta, possibly caused by a fixed electric field. Our results include the following. First, in the independent energy-offset model, we observed the emergence of commensuration effects when scanning the electron filling factor (FF) across integer values. These commensuration effects were profound as they reduced the mobility by several orders of magnitude. We analyzed these commensuration effects in a five-dimensional parameter space, as a function of the on-site charging energy E-C, energy offset Delta, disorder D, the electron FF, and temperature k(B)T. We demonstrated the complexity of our model by showing that at integer FFs commensuration effects are present in some regions of the parameter space, while they vanish in other regions, thus defining distinct dynamical phases of the model. We determined the phase boundaries between these dynamical phases. Second, using these results as a foundation, we shifted our focus to the experimentally much-studied NP-FETs. NP-FETs are also characterized by an interlayer energy offset Delta, which, in contrast to our first model, is set by the gate voltage V-G and thereby related to the electron FF. We repeated many of our simulations and again demonstrated the emergence of commensuration effects and distinct dynamical phases in these NP-FETs. Notably, the commensuration effects in the NP-FETs showed many similarities to those in the independent energy-offset BNS.

Qu, Luman↗
NASA NTRS1985

Hybrid power semiconductor

The voltage rating of a bipolar transistor may be greatly extended while at the same time reducing its switching time by operating it in conjunction with FETs in a hybrid circuit. One FET is used to drive the bipolar transistor while the other FET is connected in series with the transistor and an inductive load. Both FETs are turned on or off by a single drive signal of load power, the second FET upon ceasing conductions, rendering one power electrode of the bipolar transistor open. Means are provided to dissipate currents which flow after the bipolar transistor is rendered nonconducting.

Chen, D. Y.↗
NASA NTRS2008

Disabling CNT Electronic Devices by Use of Electron Beams

Bombardment with tightly focused electron beams has been suggested as a means of electrically disabling selected individual carbon-nanotubes (CNTs) in electronic devices. Evidence in support of the suggestion was obtained in an experiment in which a CNT field-effect transistor was disabled (see figure) by focusing a 1-keV electron beam on a CNT that served as the active channel of a field-effect transistor (FET). Such bombardment could be useful in the manufacture of nonvolatile-memory circuits containing CNT FETs. Ultimately, in order to obtain the best electronic performances in CNT FETs and other electronic devices, it will be necessary to fabricate the devices such that each one contains only a single CNT as an active element. At present, this is difficult because there is no way to grow a single CNT at a specific location and with a specific orientation. Instead, the common practice is to build CNTs into electronic devices by relying on spatial distribution to bridge contacts. This practice results in some devices containing no CNTs and some devices containing more than one CNT. Thus, CNT FETs have statistically distributed electronic characteristics (including switching voltages, gains, and mixtures of metallic and semiconducting CNTs). According to the suggestion, by using a 1-keV electron beam (e.g., a beam from a scanning electron microscope), a particular nanotube could be rendered electrically dysfunctional. This procedure could be repeated as many times as necessary on different CNTs in a device until all of the excess CNTs in the device had been disabled, leaving only one CNT as an active element (e.g., as FET channel). The physical mechanism through which a CNT becomes electrically disabled is not yet understood. On one hand, data in the literature show that electron kinetic energy >86 keV is needed to cause displacement damage in a CNT. On the other hand, inasmuch as a 1-keV beam focused on a small spot (typically a few tens of nanometers wide) deposits a significant amount of energy in a small volume, the energy density may suffice to thermally induce structural and/or electronic changes that disable the CNT. Research may be warranted to investigate this effect in detail.

Petkov, Mihail↗
DOE OSTI2020

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

42 ENGINEERING↗
DOE OSTI2021

Molecular Engineering of 2D Nanomaterial Field-Effect Transistor Sensors: Fundamentals and Translation across Innovation Spectrum

We report over the last decade, 2D layered nanomaterials have attracted significant attention across the scientific community due to their rich and exotic properties. Various nanoelectronic devices based on these 2D nanomaterials have been explored and demonstrated, including those for environmental applications. Here, the fundamental attributes of 2D layered nanomaterials for field-effect transistor (FET) sensors and tunneling FET (TFET) sensors, which provide versatile detection of water contaminants such as heavy-metal ions, bacteria, nutrients, and organic pollutants, are discussed. The major challenges and opportunities are also outlined for designing and fabricating 2D nanomaterial FET/TFET sensors with superior performance. Translation of these FET/TFET sensors from fundamental research to applied technology is illustrated through a case study on graphene-based real-time FET water sensors. A second case study centers on large-scale sensor networks for water-quality monitoring to enable intelligent drinking water and river-water systems. Overall, 2D nanomaterial FET sensors have significant potential for enabling a human-centered intelligent water system that can likely be applied to other precarious water supplies around the globe.

2D nanomaterials↗