Search NASA⌕ Search

SEARCH · Search NASA

Results for “LOGIC PROGRAMMING”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 127 records · Page 7

Navigating Large Chemical Spaces Using Graph Theory and Integer Programming

Navigating and analyzing large chemical spaces are necessary to accelerate the design and discovery of new molecules and chemical processes. In this work, we introduce a computational framework that integrates graph theory and integer programming to enable the efficient navigation of large chemical spaces. Our framework represents the chemical space as a graph, wherein nodes represent molecules and edges represent the degree of similarity or connectivity based on domain-specific information. Using the graph representation, we identify representative molecules by computing the so-called minimum dominating set (MDS), which in our context is the minimum set of molecules that is connected to all other molecules. We present a suite of solution strategies for the MDS problem including heuristic and rigorous integer programming (IP) approaches. We show that these approaches allow us to capture physicochemical properties and domain-specific logic and constraints, facilitating the identification of molecules with the target properties. We demonstrate the effectiveness of the proposed approach by navigating the chemical space of per- and polyfluoroalkyl substances (PFAS); this comprises approximately 15,000 molecular structures. We compare our framework against traditional dimensionality reduction and clustering methods such as t-SNE and K-means clustering.

Chemical structure↗

Characterization of Quantum Frequency Processors

Frequency-bin qubits possess unique synergies with wavelength-multiplexed lightwave communications, suggesting valuable opportunities for quantum networking with the existing fiber-optic infrastructure. Although the coherent manipulation of frequency-bin states requires highly controllable multi-spectral-mode interference, the quantum frequency processor (QFP) provides a scalable path for gate synthesis leveraging standard telecom components. Here, we summarize the state of the art in experimental QFP characterization. Distinguishing between physically motivated “open box” approaches that treat the QFP as a multiport interferometer, and “black box” approaches that view the QFP as a general quantum operation, we highlight the assumptions and results of multiple techniques, including quantum process tomography of a tunable beamsplitter—to our knowledge the first full process tomography of any frequency-bin operation. Our findings should inform future characterization efforts as the QFP increasingly moves beyond proof-of-principle tabletop demonstrations toward integrated devices and deployed quantum networking experiments.

42 ENGINEERING↗

Method and apparatus for maintaining data coherence in a non-uniform compute device

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

97 MATHEMATICS AND COMPUTING↗

A Pulse Generation Framework with Augmented Program-aware Basis Gates and Criticality Analysis

Near-term intermediate scale quantum (NISQ) de- vices are subject to considerable noise and short coherence time. Consequently, it is critical to minimize circuit execution latency. Traditionally, each basis gate of a transpiled circuit is decoded into a fixed episode of the device control pulses. Recently, people started to investigate merged pulse generation for customized gates through quantum optimal control (QOC). However, existing QOC approaches face the challenges of (i) restricted search space due to prohibitive compilation overhead; (ii) suboptimal end-to-end performance due to aggressive local optimization and falsely introduced dependency among the customized gates; (iii) inadequate adaptivity towards system calibration, which is critical for NISQ devices. In this work, we propose PAQOC, a novel QOC framework that can (i) automatically detect frequently encountered gate patterns in the logical circuit by modeling the problem as a subgraph mining process and reuse these patterns to enable much larger search space exploration (i.e., program aware); (ii) systemically construct customized gate-set based on the impact to the overall program latency (i.e., criticality-aware); and (iii) quickly adapt to system re-calibration thanks to the small-scale pattern-based gate generation (i.e., adaptivity-aware). PAQOC achieves a good tradeoff between circuit performance and compilation time, allowing fully automatic, single stop, ad- hoc customized pulse generation for more efficient execution of user programs on NISQ devices. Evaluations using fifteen applications show that PAQOC can achieve on average 1.95× speedup of the circuit latency and achieve on average 36.7% reduction in compilation overhead. With PAQOC, circuits can run faster with reduced noise, allowing deeper circuits to be tested within the coherence time of present NISQ platforms.

Chen, Yanhao↗

Data Quality Objectives Supporting the Environmental Direct Radiation Monitoring Program for the Idaho National Laboratory

This document presents the development of the data quality objectives (DQOs) for the Idaho National Laboratory (INL) Environmental Direct Radiation Monitoring Program and follows the Environmental Protection Agency (EPA) DQO process (EPA 2006). This document also develops and presents the logic to determine the specific number of direct radiation monitoring locations around INL facilities on the desert west of Idaho Falls and in Idaho Falls, at locations bordering the INL Site, and in the surrounding regional area. The selection logic follows the guidance from the Department of Energy (DOE) (2015) for environmental surveillance of DOE facilities.

54 ENVIRONMENTAL SCIENCES↗

Approximate error conjugation gradient minimization methods

In one embodiment, a method includes selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, calculating an approximate error using the subset of rays, and calculating a minimum in a conjugate gradient direction based on the approximate error. In another embodiment, a system includes a processor for executing logic, logic for selecting a subset of rays from a set of all rays to use in an error calculation for a constrained conjugate gradient minimization problem, logic for calculating an approximate error using the subset of rays, and logic for calculating a minimum in a conjugate gradient direction based on the approximate error. In other embodiments, computer program products, methods, and systems are described capable of using approximate error in constrained conjugate gradient minimization problems.

97 MATHEMATICS AND COMPUTING↗

Controlling accesses to a branch prediction unit for sequences of fetch groups

An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

Yalavarti, Adithya↗

Development of an Energy Services Interface for the EGoT

The Energy Services Interface (ESI) is a set of rules that ensure private, secure, and trustworthy information exchange between Grid Service Providers (GSPs) and utility customers. Large-scale adoption of Distributed Energy Resources (DERs) will be necessary for GSPs to dispatch effective grid services, and to stimulate technological innovations in DER and DERMS (DER Management Systems) technologies, as well as novel grid service programs. The ESI promotes these objectives by advancing a set of rules and interoperability requirements that define bi-directional, service-oriented, logical interfaces between GSPs and customers’ DERs, with expectations for privacy, security, and trust. The ESI rules and interoperability requirements establish boundaries between customers and GSPs that delineate the functions and responsibilities that must be implemented by the developers of Energy Grid of Things (EGoT) ecosystem products. These rules impose constraints on the implementation of a DERMS. The ESI interoperability requirements are based on the Interoperability Maturity Model (IMM), developed by the Grid Modernization Laboratory Consortium. By emphasizing private, secure, and trustworthy information exchange, and by mandating a service-oriented and interoperable architecture, the ESI promotes the development of an EGoT ecosystem that motivates customer participation and technological innovation. Interoperability will encourage innovation by reducing barriers to entry and increasing confidence of stakeholders. Customers will be willing to participate in DER service programs that establish trust and emphasize customer choice. Large-scale customer participation ensures GSPs have ample DER resources to provide grid services that have significant impact on grid reliability and reduce electricity cost for consumers. This in turn signals economic opportunities that encourage innovation, resulting in the development of a robust EGoT ecosystem.

24 POWER TRANSMISSION AND DISTRIBUTION↗

FTTN: Feature-Targeted Testing for Numerical Properties of NVIDIA & AMD Matrix Accelerators

While NVIDIA has been the dominant provider of GPUs for HPC and ML, now AMD has several offerings of GPUs. This encourages programmers to try out AMD GPUs for new codes and also port existing codes over. Unfortunately, without understanding the floating-point differences between these GPU types, software development or porting can introduce bugs—and currently such an understanding is lacking. The magnitude of this open question becomes clear if one imagines the the number of floating-point precision choices (FP16, FP32, etc.), floating-point formats (standard floats, brain-float, etc.), and execution units available (elementary units, matrix/tensor cores, etc.) Questions such as rounding modes and subnormal support are also important. Most of these answers are unknown today or are hard to access. We provide the first testing-guided approach that answers a significant number of these questions. We also devise tests to reveal internal information (e.g., extra bits kept) to make sure that our findings are reliable. Many of our tests employ systematically generated random-programs, others apply fast-math flags and some involve fused multiplyadd. Especially for tensor/matrix cores, the tests have nontrivial logic that we present Our testing approach is reusable for the plethora of GPUs yet to be introduced. Our findings include up to 7 ulps of difference between NVIDIA and AMD for sin and cos at FP32 precision and 3 ulp at FP64. In our study of matrix cores (NVIDIA) and tensor cores (AMD), we have extensively characterized rounding modes (truncation versus round-to-nearest), the number of extra internal bits kept (whether 3 bits are kept or not), subnormal support for inputs and outputs across four different floating-point formats and across NVIDIA A100 and AMD MI250X GPUs. We believe that this wealth of data becoming available for the first time may help avoid significant porting bugs when migrating code across these platforms.

Li, Xinyi↗

Arbitration in crossbar interconnect for low latency

A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.

97 MATHEMATICS AND COMPUTING↗

Failure detection in high-performance clusters and computers using chaotic map computations

A programmable media includes a processing unit capable of independent operation in a machine that is capable of executing 10.sup.18 floating point operations per second. The processing unit is in communication with a memory element and an interconnect that couples computing nodes. The programmable media includes a logical unit configured to execute arithmetic functions, comparative functions, and/or logical functions. The processing unit is configured to detect computing component failures, memory element failures and/or interconnect failures by executing programming threads that generate one or more chaotic map trajectories. The central processing unit or graphical processing unit is configured to detect a computing component failure, memory element failure and/or an interconnect failure through an automated comparison of signal trajectories generated by the chaotic maps.

97 MATHEMATICS AND COMPUTING↗

Automated radiotherapy treatment plan integrity verification

Purpose: In our clinic, physicists spend from 15 to 60 min to verify the physical and dosimetric integrity of radiotherapy plans before presentation to radiation oncology physicians for approval. The purpose of this study was to design and implement a framework to automate as many elements of this quality control (QC) step as possible. Methods: A comprehensive computer application was developed to carry out a majority of these verification tasks in the Philips PINNACLE treatment planning system (TPS). This QC tool functions based on both PINNACLE scripting elements and PERL sub-routines. The core of this technique is the method of dynamic scripting, which involves a PERL programming module that is flexible and powerful for treatment plan data handling. Run-time plan data are collected, saved into temporary files, and analyzed against standard values and predefined logical rules. The results were summarized in a hypertext markup language (HTML) report that is displayed to the user. Results: This tool has been in clinical use for over a year. The occurrence frequency of technical problems, which would cause delays and suboptimal plans, has been reduced since clinical implementation. Conclusions: In addition to drastically reducing the set of human-driven logical comparisons, this QC tool also accomplished some tasks that are otherwise either quite laborious or impractical for humans to verify, e.g., identifying conflicts amongst IMRT optimization objectives.

62 RADIOLOGY AND NUCLEAR MEDICINE↗

Pressurizer dynamic model and emulated programmable logic controllers for nuclear power plants cybersecurity investigations

This work demonstrates the functionality of the pressurizer using a fast-running three regions, non-equilibrium model and control programs of emulated PLCs. The state variables from an integrated model of primary loop in a representative PWR plant are communicated to the pressurizer’s emulated PLCs using a synchronized data transfer function. In turn, the PLCs communicate back instructions to the pressurizer model to adjust the pressure and water level to remain within preprogramed setpoints. Pressurizer model simultaneously solves the coupled mass and energy conservation equations in the saturated vapor and saturated and subcooled liquid regions using fixed step solver. Results demonstrate the response of the pressurizer model linked to an emulated pressure and water level PLCs in a simulated transient involving surge-in and surge-out events. The 50 ms response delay time for the emulated PLC insignificantly affects operation and predictions of the pressurizer model.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

Supply Chain Binary Program Assessment Annual Report

Secure environments face a steadily increasing threat from the introduction of scientific equipment that includes extensive software components. Devices such as powerful microscopes, 3d printers, programmable logic controllers, and many others, increase our capability and scientific output. Unfortunately, they now frequently include an entire computing stack with custom software bundled along with entire operating systems. Our ability to introspect and understand binary software is extremely limited, opening up the possibility of malicious third-parties including software that compromises our critical missions.

42 ENGINEERING↗

Automated Behavior Computation for Software Analysis and Validation

Software systems can exhibit massive numbers of possi-ble execution paths, and even the most comprehensive testing can exercise only a small fraction of these. It is no surprise that systems experience errors and vulnerabilities in field use when most executions are untested. While the problem seems intractable at the execution level, it may not be so at the functional semantics level. Structured programs are expressed in a finite hierarchy of control structures, each of which corresponds to a mathematical function or relation. A correctness theo-rem defines transformation of these structures from procedural logic into non-procedural, as-built specifications of behavior. These specifications enumerate behavior for all circumstances of use and cover the behav-ior space. Automation of these computations affords a new means for validating software functionality and security properties. This paper describes theory and implementation for loop behavior computation in pa-ticular, and illustrates use of an automated behavior computation system to validate a miniature program with and without embedded malware.

99 GENERAL AND MISCELLANEOUS↗

Boosting RDataFrame performance with transparent bulk event processing

RDataFrame is ROOT’s high-level interface for Python and C++ data analysis. Since it first became available, RDataFrame adoption has grown steadily and it is now poised to be a major component of analysis software pipelines for LHC Run 3 and beyond. Thanks to its design inspired by declarative programming principles, RDataFrame enables the development of highperformance, highly parallel analyses without requiring expert knowledge of multi-threading and I/O: user logic is expressed in terms of self-contained, small computation kernels tied together by a high-level API. This design completely decouples analysis logic from its actual execution, and opens several interesting avenues for workflow optimization. In particular, in this work we explore the benefits of moving internal data processing from an event-by-event to a bulkby-bulk loop. This refactoring dramatically reduces the framework’s runtime overheads; in collaboration with the I/O layer it improves data access patterns; it exposes information that optimizing compilers might use to auto-vectorize the invocation of user-defined computations; finally, while existing user-facing interfaces remain unaffected, it becomes possible to additionally offer interfaces that explicitly expose bulks of events, useful e.g. for the injection of GPU kernels into the analysis workflow. In order to inform similar future R&D, design challenges will be presented, as well as an investigation of the relevant timememory trade-off backed by novel performance benchmarks.

Guiraud, Enrico↗

Exploiting communication concurrency on high performance computing systems

Although logically available, applications may not exploit enough instantaneous communication concurrency to maximize hardware utilization on HPC systems. This is exacerbated in hybrid programming models such as SPMD+OpenMP. We present the design of a "multi-threaded" runtime able to transparently increase the instantaneous network concurrency and to provide near saturation bandwidth, independent of the application configuration and dynamic behavior. The runtime forwards communication requests from application level tasks to multiple communication servers. Our techniques alleviate the need for spatial and temporal application level message concurrency optimizations. Experimental results show improved message throughput and bandwidth by as much as 150% for 4KB bytes messages on InfiniBand and by as much as 120% for 4KB byte messages on Cray Aries. For more complex operations such as all-to-all collectives, we observe as much as 30% speedup. This translates into 23% speedup on 12,288 cores for a NAS FT implemented using FFTW. We also observe as much as 76% speedup on 1,500 cores for an already optimized UPC+OpenMP geometric multigrid application using hybrid parallelism.

97 MATHEMATICS AND COMPUTING↗

GaN HEMT Fabrication for Radiation-Hardened Sensing and Communications Electronics

Gallium nitride (GaN), a wide bandgap semiconductor, has vast potential to address two environment conditions associated with the application of electronics to nuclear power: elevated temperatures, and high levels of radiation. A process was developed at The Ohio State University (OSU) to enable fabrication of complex digital and analog electronics circuits for application to nuclear power environments such as locations near or in the reactor core or in spent nuclear fuel casks. Radio frequency (RF)-grade GaN high electron mobility transistor (HEMT) devices were fabricated as part of this process. These were fabricated as depletion mode and enhancement mode devices. They have been electrically characterized and have demonstrated the expected performance. Behavioral models (Verilog-A) were developed from these device measurements to enable electrical simulation of GaN HEMT devices and circuits using common electronics simulation tools based on Simulation Program with Integrated Circuit Emphasis (SPICE). A similar set of GaN HEMT devices is being developed to provide lower speed devices for logic and analog functions. These accomplishments position this technology for effective application to sensor interfacing, signal processing, and data communications in nuclear power plants, including operation in or near the reactor core.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗