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At least 127 records · Page 7

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NASA NTRS2011

Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

Harper, Michael↗

DOE OSTI2023

Engineering activatable promoters for scalable and multi-input CRISPRa/i circuits

Dynamic, multi-input gene regulatory networks (GRNs) are ubiquitous in nature. Multilayer CRISPR-based genetic circuits hold great promise for building GRNs akin to those found in naturally occurring biological systems. We develop an approach for creating high-performing activatable promoters that can be assembled into deep, wide, and multi-input CRISPR-activation and -interference (CRISPRa/i) GRNs. By integrating sequence-based design and in vivo screening, we engineer activatable promoters that achieve up to 1,000-fold dynamic range in an Escherichia coli-based cell-free system. These components enable CRISPRa GRNs that are six layers deep and four branches wide. We show the generalizability of the promoter engineering workflow by improving the dynamic range of the light-dependent EL222 optogenetic system from 6-fold to 34-fold. Additionally, high dynamic range promoters enable CRISPRa systems mediated by small molecules and protein–protein interactions. We apply these tools to build input-responsive CRISPRa/i GRNs, including feedback loops, logic gates, multilayer cascades, and dynamic pulse modulators. Our work provides a generalizable approach for the design of high dynamic range activatable promoters and enables classes of gene regulatory functions in cell-free systems.

42 ENGINEERING↗

DOE OSTI2023

Discovery of the Azaserine Biosynthetic Pathway Uncovers a Biological Route for α‐Diazoester Production

Abstract Azaserine is a bacterial metabolite containing a biologically unusual and synthetically enabling α‐diazoester functional group. Herein, we report the discovery of the azaserine ( aza ) biosynthetic gene cluster from Glycomyces harbinensis . Discovery of related gene clusters reveals previously unappreciated azaserine producers, and heterologous expression of the aza gene cluster confirms its role in azaserine assembly. Notably, this gene cluster encodes homologues of hydrazonoacetic acid (HYAA)‐producing enzymes, implicating HYAA in α‐diazoester biosynthesis. Isotope feeding and biochemical experiments support this hypothesis. These discoveries indicate that a 2‐electron oxidation of a hydrazonoacetyl intermediate is required for α‐diazoester formation, constituting a distinct logic for diazo biosynthesis. Uncovering this biological route for α‐diazoester synthesis now enables the production of a highly versatile carbene precursor in cells, facilitating approaches for engineering complete carbene‐mediated biosynthetic transformations in vivo.

Van Cura, Devon↗

DOE OSTI2023

Discovery of the Azaserine Biosynthetic Pathway Uncovers a Biological Route for α‐Diazoester Production

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

DOE OSTI2026

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗

DOE OSTI2022

Chapter 10: Advances in Protein Engineering and its Application in Synthetic Biology

Protein engineering has been used successfully in fields ranging from medicine to food science to biofuels. Applications of protein engineering include developing antiviral peptides or other protein therapeutics, antibody engineering, designing protein-based logic circuits, engineering enzymes to be more specific or to function under industrially relevant conditions such as at higher temperatures or high/low pH, modifying cell signaling or regulatory functions, and so on. Advances in recombinant DNA, "omics," and CRISPR-Cas (clustered regularly interspaced short palindromic repeats and its associated proteins) technologies, combined with high-throughput screening facilities, will lead to improved methods for protein engineering, enabling easy modification of more proteins/enzymes for new specific applications. New methods for rational design, directed evolution, and computer-aided protein design will further accelerate the speed of protein evolution and expand the scope for protein engineering. In this chapter we discuss general protein engineering strategies and advances in engineering proteins with desired functions, focusing on the "design" and "build" part of the design-build-test-learn cycle.

BIOMASS FUELS↗

NASA NTRS2004

Digital logic optimization using selection operators

According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more.

Whitaker, Sterling R.↗

NASA NTRS1989

Optical Addressing And Clocking Of RAM's

Proposed random-access-memory (RAM) addressing system, in which memory linked optically to read/write logic circuits, greatly increases computer operating speed. System - comprises addressing circuits including numerous lasers as signal sources, numerous optical gates including optical detectors associated with memory cells, and holographic element to direct light signals to desired memory-cell locations - applied to high-capacity digital systems, supercomputers, and complex microcircuits.

Johnston, Alan R.↗

NASA NTRS1993

Reconfigurable fuzzy cell

This invention relates to a reconfigurable fuzzy cell comprising a digital control programmable gain operation amplifier, an analog-to-digital converter, an electrically erasable PROM, and 8-bit counter and comparator, and supporting logic configured to achieve in real-time fuzzy systems high throughput, grade-of-membership or membership-value conversion of multi-input sensor data. The invention provides a flexible multiplexing-capable configuration, implemented entirely in hardware, for effectuating S-, Z-, and PI-membership functions or combinations thereof, based upon fuzzy logic level-set theory. A membership value table storing 'knowledge data' for each of S-, Z-, and PI-functions is contained within a nonvolatile memory for storing bits of membership and parametric information in a plurality of address spaces. Based upon parametric and control signals, analog sensor data is digitized and converted into grade-of-membership data. In situ learn and recognition modes of operation are also provided.

Salazar, George A.↗

NASA NTRS1992

Reconfigurable Fuzzy Cell

Flexible sensor-signal-processing circuit responds rapidly. Reconfigurable fuzzy cell provides real-time, high-throughput, interrupt-driven, multiplex conversion of sample raw signals from sensors into their grade of membership for use in fuzzy-logic control system.

Salazar, George A.↗

NASA NTRS2007

Space Shuttle Stiffener Ring Foam Failure, a Non-Conventional Approach

The Space Shuttle makes use of the excellent properties of rigid polyurethane foam for cryogenic tank insulation and as structural protection on the solid rocket boosters. When foam applications debond, classical methods of analysis do not always provide root cause of the failure of the foam. Realizing that foam is the ideal media to document and preserve its own mode of failure, thin sectioning was seen as a logical approach for foam failure analysis. Thin sectioning in two directions, both horizontal and vertical to the application, was chosen to observe the three dimensional morphology of the foam cells. The cell foam morphology provided a much greater understanding of the failure modes than previously achieved.

Howard, Philip M.↗

NASA NTRS1989

Asymmetrical SRAM Cells For Radiation Tests

Features of circuits altered to increase or decrease sensitivity to radiation. State-space analysis used to analyze single-event-upset behavior of memory cell. When voltage on node a is set at one of indicated initial values Vao and then released, voltages on nodes a and b then follow indicated trajectory to final logic "one" or logic "zero" state. Ability to do this important for design of radiation-detecting integrated circuits (deliberately made more sensitive to ionizing radiation) and "radiation-hardened" integrated circuits - those intended to be relatively invulnerable to intense radiation.

Buehler, Martin G.↗

DOE OSTI2025

Harnessing ferro-valleytricity in pentalayer rhombohedral graphene for memory and compute

Two-dimensional materials with multiple degrees of freedom, including spin, valleys, and orbitals, open up an exciting avenue for engineering multifunctional devices. Beyond spintronics, these degrees of freedom can lead to novel quantum effects such as valley-dependent Hall effects and orbital magnetism, which could revolutionize next-generation electronics. However, achieving independent control over valley polarization and orbital magnetism has been a challenge due to the need for large electric fields. A recent breakthrough involving pentalayer rhombohedral graphene has demonstrated the ability to individually manipulate anomalous Hall signals and orbital magnetic hysteresis, forming what is known as a valley-magnetic quartet. Here, we leverage the electrically tunable ferro-valleytricity of pentalayer rhombohedral graphene to develop nonvolatile memory and in-memory computation applications. We propose an architecture for a dense, scalable, and selector-less nonvolatile memory array that harnesses the electrically tunable ferro-valleytricity. In our designed array architecture, nondestructive read and write operations are conducted by sensing the valley state through two different pairs of terminals, allowing for independent optimization of read/write peripheral circuits. The power consumption of our PRG-based array is remarkably low, with only ∼6 nW required per write operation and ∼2.3 nW per read operation per cell. This consumption is orders of magnitude lower than that of the majority of state-of-the-art cryogenic memories. Additionally, we engineer in-memory computation by implementing majority logic operations within our proposed nonvolatile memory array without modifying the peripheral circuitry. In conclusion, our framework presents a promising pathway toward achieving ultra-dense cryogenic memory and in-memory computation capabilities.

2D materials↗

NASA NTRS1998

The Design and Development of the SMEX-Lite Power System

This paper describes the design and development of a 250W orbit average electrical power system electronic Power Node and software for use in Low Earth Orbit missions. The mass of the Power Node is 3.6 Kg (8 lb.). The dimensions of the Power Node are 30cm x 26cm x 7.9cm (11 in. x 10.25 in x 3.1 in.) The design was realized using software, Field Programmable Gate Array (FPGA) digital logic and surface mount technology. The design is generic enough to reduce the non-recurring engineering for different mission configurations. The Power Node charges one to five, low cost, 22-cell 4 AH D-cell battery packs independently. The battery charging algorithms are executed in the power software to reduce the mass and size of the power electronic. The Power Node implements a peak-power tracking algorithm using an innovative hardware/software approach. The power software task is hosted on the spacecraft processor. The power software task generates a MIL-STD-1553 command packet to update the Power Node control settings. The settings for the battery voltage and current limits, as well as minimum solar array voltage used to implement peak power tracking are contained in this packet. Several advanced topologies are used in the Power Node. These include synchronous rectification in the bus regulators, average current control in the battery chargers and quasi-resonant converters for the Field Effect Transistor (FET) transistor drive electronics. Lastly, the main bus regulator uses a feed-forward topology with the PWM implemented in an FPGA.

Rakow, Glenn P.↗

NASA NTRS2018

Grasp Assist Device with Automatic Mode Control Logic

A system includes a glove, sensors, actuator assemblies, and controller. The sensors include load sensors which measure an actual grasping force and attitude sensors which determine a glove attitude. The actuator assembly provides a grasp assist force to the glove. Respective locations of work cells in the work environment and permitted work tasks for each work cell are programmed into the controller. The controller detects the glove location and attitude. A work task is selected by the controller for the location. The controller calculates a required grasp assist force using measured actual grasping forces from the load sensors. The required grasp assist force is applied via the glove using the actuator assembly to thereby assist the operator in performing the identified work task.

Davis, Donald R.↗

NASA NTRS1999

SRAM Based Re-programmable FPGA for Space Applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Wang, J. J.↗

NASA NTRS1985

An investigation of arc discharging on negatively biased dielectric conductor samples in a plasma

Proposals are now being developed for the construction of high-power photovoltaic systems for operation in low Earth orbit, where the plasma number density is about 1,000 to 1,000,000 per cubic cm. Existing data indicate that interactions between the plasma and high-voltage surfaces of an orbiting power system will occur. In ground tests, where the applied voltage is increased negatively from ground, the array current collection shows an approximately linear rise until it terminates in arcing at greater than several hundred volts negative. This arcing may reduce the power generation efficiency and could possibly affect the low-level logic circuits of the spacecraft. Therefore it is important that the arcing phenomenon be well understood. This study is a survey of the behavior of different dielectric-conductor samples, including a solar cell module, that were biased negatively in a low-density plasma environment with the intent of defining arc discharge conditions and characteristics. Procedures and results are discussed.

Miller, W. L.↗

NASA NTRS2017

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Katz, Richard B.↗