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Results for “MOS transistor”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Accumulation-Type Ohmic van der Waals Contacts to Nearly Intrinsic WSe 2 Nanosheet-Based Channels: Implications for Field-Effect Transistors

We report the fabrication of ohmic van der Waals (vdW) contacts to nearly intrinsic WSe 2 nanosheet-based channels in field-effect transistors (FETs) using degenerately p-doped MoS2 (p + -MoS2) as a contact metal. We demonstrate that accumulation-type ohmic contacts and the high device performance are achievable without electrostatically gating the drain/source contact regions despite the nearly intrinsic nature of WSe 2 . Back-gated WSe 2 FETs with p + -MoS 2 bottom contacts (which screen the back-gate electric field in the drain/source regions) exhibit linear output characteristics, a high on/off ratio of 10 8 , and a high two-terminal field-effect mobility up to ~200 cm2 V –1 s –1 at room temperature. Our theoretical modeling reveals that the p + -MoS 2 /WSe 2 vdW junction behaves like a metal/semiconductor ohmic contact signified by a vanishingly thin space-charge region of ~1 nm on the p + -MoS 2 side and a substantial accumulation layer of free holes on the WSe 2 side, which is further verified by additional temperature-dependent and dual-gated measurements of WSe 2 FETs. We attribute the formation of accumulation-type ohmic contacts free of a Schottky barrier to the near absence of Fermi-level pinning at the vdW interface and the work function of p + -MoS 2 being larger than the ionization energy of WSe 2 . This study represents an important step toward achieving low-resistance ohmic contacts to two-dimensional (2D) semiconductors by eliminating the Fermi-level pinning effects, which is expected to have significant implications for next-generation 2D semiconductor-based nanoelectronics.

36 MATERIALS SCIENCE↗
NASA NTRS2010

Modeling a Common-Source Amplifier Using a Ferroelectric Transistor

This paper presents a mathematical model characterizing the behavior of a common-source amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the common-source amplifier is the most widely used amplifier in MOS technology, understanding and modeling the behavior of the FeFET-based common-source amplifier will help in the integration of FeFETs into many circuits.

Sayyah, Rana↗
NASA NTRS1983

Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

Brucker, G. J.↗
NASA NTRS1980

Oxidation of gallium arsenide in a plasma multipole device. Study of the MOS structures obtained

The oxygen plasma oxidation of GaAs was studied in order to obtain extremely high frequency responses with MOS devices. In the multipole system a homogeneous oxygen plasma of high density can easily be obtained in a large volume. This system is thus convenient for the study of plasma oxidation of GaAs. The electrical properties of the MOS diodes obtained in this way are controlled by interface states, located mostly in the upper half of the band gap where densities in the 10 to the 13th power/(sq cm) (eV) range can be estimated. Despite these interface states the possibility of fabricating MOSFET transistors working mostly in the depletion mode for a higher frequency cut-off still exists.

Gourrier, S.↗
NASA NTRS1986

Submicron Silicon MOSFET

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

Daud, T.↗
NASA NTRS1992

Silicon device performance measurements to support temperature range enhancement

Characterization results of a MOS controlled thyristor (MCTA60P60) are presented. This device is rated for 60A and for an anode to cathode voltage of -600 V. As discussed in the last report, the MCT failed during 500 V leakage tests at 200 C. In contrast to the BJT (bipolar junction transistor), MOSFET, and IGBT (insulated gate bipolar transistor) devices tested, the breakdown voltage of the MCT decreases significantly with increasing temperature.

Bromstead, James↗
DOE OSTI2024

Size Effect of Negative Capacitance State and Subthreshold Swing in Van der Waals Ferrielectric Field–Effect Transistors

Analytical calculations corroborated by the finite element modeling show that thin films of Van der Waals ferrielectrics covered by a 2D-semiconductor are promising candidates for the controllable reduction of the dielectric layer capacitance due to the negative capacitance (NC) effect emerging in the thin films. The NC state is conditioned by energy-degenerated poly-domain states of the ferrielectric polarization induced in the films under incomplete screening conditions in the presence of a dielectric layer. Calculations performed for the FET-type heterostructure “ferrielectric CuInP 2 S 6 film—2D-MoS 2 single-layer—SiO 2 dielectric layer” reveal the pronounced size effect of the multilayer capacitance. Derived analytical expressions for the electric polarization and multilayer capacitance allow to predict the thickness range of the dielectric layer and ferrielectric film for which the NC effect is the most pronounced in various Van der Waals ferrielectrics, and the corresponding subthreshold swing becomes much less than the Boltzmann's limit. Obtained results can be useful for the size and temperature control of the NC effect in the steep-slope ferrielectric FETs.

36 MATERIALS SCIENCE↗
NASA NTRS1993

Design of power electronics for TVC EMA systems

The Composite Development Division of the Propulsion Laboratory at Marshall Space Flight Center (MSFC) is currently developing a class of electromechanical actuators (EMA's) for use in space transportation applications such as thrust vector control (TVC) and propellant control valves (PCV). These high power servomechanisms will require rugged, reliable, and compact power electronic modules capable of modulating several hundred amperes of current at up to 270 volts. MSFC has selected the brushless dc motor for implementation in EMA's. This report presents the results of an investigation into the applicability of two new technologies, MOS-controlled thyristors (MCT's) and pulse density modulation (PDM), to the control of brushless dc motors in EMA systems. MCT's are new power semiconductor devices, which combine the high voltage and current capabilities of conventional thyristors and the low gate drive requirements of metal oxide semiconductor field effect transistors (MOSFET's). The commanded signals in a PDM system are synthesized using a series of sinusoidal pulses instead of a series of square pulses as in a pulse width modulation (PWM) system. A resonant dc link inverter is employed to generate the sinusoidal pulses in the PDM system. This inverter permits zero-voltage switching of all semiconductors which reduces switching losses and switching stresses. The objectives of this project are to develop and validate an analytical model of the MCT device when used in high power motor control applications and to design, fabricate, and test a prototype electronic circuit employing both MCT and PDM technology for controlling a brushless dc motor.

Nelms, R. Mark↗
NASA NTRS1992

Silicon device performance measurements to support temperature range enhancement

Testing of the metal oxide semiconductor (MOS)-controlled thyristor (MCT) has uncovered a failure mechanism at elevated temperature. The failure appears to be due to breakdown of the gate oxide. Further testing is underway to verify the failure mode. Higher current level inverters were built to demonstrate 200 C operation of the N-MOSFET's and insulated-gate-bipolar transistors (IGBT's) and for life testing. One MOSFET failed early in testing. The origin of this failure is being studied. No IGBT's have failed. A prototype 28-to-42 V converter was built and is being tested at room temperature. The control loop is being finalized. Temperature stable, high value (10 micro-F) capacitors appear to be the limiting factor in the design at this time. In this application, the efficiency will be lower for the IGBT version due to the large V sub(cesat) (3.5-4 V) compared to the input voltage of 28 V. The MOSFET version should have higher efficiency; however, the MOSFET does not appear to be as robust at 200 C. Both versions are built for comparison.

Bromstead, James↗
NASA NTRS1972

Shielded silicon gate complementary MOS integrated circuit.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.↗
NASA NTRS1987

A study of charged particles/radiation damage to VLSI device materials

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Okyere, John G.↗
NASA NTRS1972

Solid state image sensing arrays

The fabrication of a photodiode transistor image sensor array in silicon, and tests on individual elements of the array are described along with design for a scanning system for an image sensor array. The spectral response of p-n junctions was used as a technique for studying the optical-absorption edge in silicon. Heterojunction structures of Sb2S3- Si were fabricated and a system for measuring C-V curves on MOS structures was built.

Sadasiv, G.↗
NASA NTRS1977

Adaptation of ion beam technology to microfabrication of solid state devices and transducers

It was found that ion beam texturing of silicon surfaces can be used to increase the effective surface area of MOS capacitors. There is, however, a problem with low dielectric breakdown. Preliminary work was begun on the fabrication of ion implanted resistors on textured surfaces and the potential improvement of wire bond strength by bonding to a textured surface. In the area of ion beam sputtering, the techniques for sputtering PVC were developed. A PVC target containing valinomycin was used to sputter an ion selective membrane on a field effect transistor to form a potassium ion sensor.

Topich, J. A.↗
NASA NTRS1982

The damage equivalence of electrons, protons, and gamma rays in MOS devices

The results of laboratory tests to determine the radiation damage effects induced on MOS devices from Co-60, electron, and proton radiation are reported. The tests are performed to establish the relationship between the Co-60 gamma rays and the level of damage to the MOS devices in regards to different damages which can be expected with the electron and particle bombardments experienced in space applications. CMOS devices were exposed to the Co-60 gamma rays, 1 MeV electrons, and 1 MeV protons while operating at 3, 10, and 15 V. The test data indicated that the Co-60 source was reliable for an initial evaluation of the electron damages up to 2 MeV charge. A correction factor was devised for transferring the Co-60 measurements to proton damages, independent of bias and transistor types, for any orbit or environment.

Brucker, G. J.↗
DOE OSTI2025

Ionic‐Liquid Free and Flexible Transistors Made of 2D Material Inks

The development of thin-film transistors (TFTs) using 2D materials is crucial for enabling scalable, low-cost, and flexible electronics. Currently, 2D TFTs with the highest performance have been achieved by using ionic-liquid gating (ILG), a technique suited for proof-of-concept studies. However, ILG suffers from slow switching speeds, temperature sensitivity, poor long-term stability, and integration challenges, making it unsuitable for practical use. Moreover, typical fabrication methods for 2D TFTs involve harsh conditions such as strong acids or high temperatures (>300 °C), limiting integration with flexible substrates. This work provides the first demonstration of an ILG-free, all-2D-material TFT fabricated onto a flexible substrate. Water-based graphene and hexagonal boron nitride (h-BN) inks are printed to deposit the electrodes and dielectric layers, respectively. The MoS 2 channel is produced via supramolecular interfacial self-assembly, yielding uniform, monolayer-rich films transferable to rigid and flexible substrates. The resulting TFTs operate below 3 V, exhibit negligible leakage current, and achieve field-effect mobilities up to 0.46 cm 2 V −1 s −1 (rising to 2.47 cm 2 V −1 s −1 with silver electrodes) measured under ambient conditions, while maintaining excellent mechanical flexibility. This work establishes a low-cost and scalable solution-processable platform for flexible electronics based on 2D materials that match requirements for practical applications.

2D materials↗
DOE OSTI2023

Influence of surface adsorption on MoS 2 memtransistor switching kinetics

Sulfur-deficient polycrystalline two-dimensional (2D) molybdenum disulfide (MoS 2 ) memtransistors exhibit gate-tunable memristive switching to implement emerging memory operations and neuromorphic computing paradigms. Grain boundaries and sulfur vacancies are critical for memristive switching; however, the underlying physical mechanisms are not fully understood. Furthermore, the adsorption of water and gaseous species strongly perturbs electronic transport in monolayer MoS 2 , and little work has been done to explore the influence of surface interactions on defect-related kinetics that produces memristive switching. Here, we study the switching kinetics of back-gated MoS 2 memtransistors using current transient measurements in a controlled atmosphere chamber. Here, we observe that adsorbed water molecules lead to suppression of the electronic trap-filling processes concomitant with the resistive switching process, resulting in altered kinetics of the resistive switching. Additionally, using the transient response from “bunched” drain voltage pulse trains performed as a function of temperature, we extract the energy of the affected trap state and find that it places the trap roughly midgap [E T = E C – 0.7 (±0.4) eV]. Our results highlight the importance of controlling for surface interactions that may affect switching kinetics in 2D memtransistors, synaptic transistors, and related memory devices.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Determining the Electronic Structure and Thermoelectric Properties of MoS 2 /MoSe 2 Type‐I Heterojunction by DFT and the Landauer Approach

Abstract The electronic structure and thermoelectric properties of MoX 2 (X = S, Se) Van der Waals heterojunctions are reported, with the intention of motivating the design of electronic devices using such materials. Calculations indicate the proposed heterojunctions are thermodynamically stable and present a band gap reduction from 1.8 eV to 0.8 eV. The latter effect is highly related to interactions between metallic d‐character orbitals and chalcogen p‐character orbitals. The theoretical approach allows to predict a transition from semiconducting to semi‐metallic behavior. The band alignment indicates a type‐I heterojunction and band offsets of 0.2 eV. Transport properties show clear n‐type nature and a high Seebeck coefficient at 300 K, along with conductivity values (σ/τ) in the order of 10 20 . Lastly, using the Landauer approach and ballistic transport, the proposed heterojunctions can be modeled as a channel material for a typical one‐gate transistor configuration predicting subthreshold values of ≈60 mV dec −1 and field–effect mobilities of ≈160 cm −2 V −1 s −1 .

López‐Galán, Oscar A.↗