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Hydrocarbon polymer coatings used in microelectronic manufacturing processes are anisotropically etched by hyperthermal atomic oxygen beams (translational energies of 0.2 to 20 eV, preferably 1 to 10 eV). Etching with hyperthermal oxygen atom species obtains highly anisotropic etching with sharp boundaries between etched and mask protected areas.
This paper presents the development of III-V based pseudomorphic high electron mobility transistors (PHEMT's) designed to operate over the temperature range 77 to 473 K (-196 to 200 C). These devices have a pseudomorphic undoped InGaAs channel that is sandwiched between an AlGaAs spacer and a buffer layer; gate widths of 200, 400, 1600, and 3200 micrometers; and a gate length of 2 micrometers. Measurements were performed at both room temperature and 473 K (200 C) and show that the drain current decreases by 30 percent and the gate current increases to about 9 microns A (at a reverse bias of -1.5 V) at the higher temperature. These devices have a maximum DC power dissipation of about 4.5 W and a breakdown voltage of about 16 V.
The device feature size continues to be on a downward trend with a simultaneous upward trend in wafer size to 300 mm. Predictive models are needed more than ever before for this reason. At NASA Ames, a Device and Process Modeling effort has been initiated recently with a view to address these issues. Our activities cover sub-micron device physics, process and equipment modeling, computational chemistry and material science. This talk would outline these efforts and emphasize the interaction among various components. The device physics component is largely based on integrating quantum effects into device simulators. We have two parallel efforts, one based on a quantum mechanics approach and the second, a semiclassical hydrodynamics approach with quantum correction terms. Under the first approach, three different quantum simulators are being developed and compared: a nonequlibrium Green's function (NEGF) approach, Wigner function approach, and a density matrix approach. In this talk, results using various codes will be presented. Our process modeling work focuses primarily on epitaxy and etching using first-principles models coupling reactor level and wafer level features. For the latter, we are using a novel approach based on Level Set theory. Sample results from this effort will also be presented.
No abstract available
A layer of germanium on a body of P type conductivity single crystal indium phosphide provides a blocking heterojunction. This device will emit light when a suitable voltage is placed thereacross or the device can be used as a photoconductor to generate electrons when light is directed thereon.
Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.
There is disclosed herein a method of making a device made up of at least two separate parts each of which is formed of a patterned array with the parts being mounted one on the other, with the patterned arrays of the parts being aligned, such as a CCD imager having a color filter thereon. The two parts are made on separate substrates with a first alignment key being formed on each substrate. The first alignment keys are formed by photolithography using the same mask to form the first alignment keys on each substrate. The various features of each of the parts are then formed on each substrate with each feature being formed by a photolithographic step using a mask which is aligned to a first alignment key so as to align all the features. A second alignment key is formed on each substrate and is positioned on each substrate in the same relationship with a first alignment key. The second alignment keys are of a material and construction so as to be visible when radiation of a desired wavelength is directed through the substrates. A part formed on one of the substrates is placed over a part formed on the other substrate. Radiation is directed through the substrates and the second alignment keys are aligned so as to align the patterned array of the two parts.
In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.
In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.
Prognostics is an engineering discipline that focuses on estimation of the health state of a component and the prediction of its remaining useful life (RUL) before failure. Health state estimation is based on actual conditions and it is fundamental for the prediction of RUL under anticipated future usage. Failure of electronic devices is of great concern as future aircraft will see an increase of electronics to drive and control safety-critical equipment throughout the aircraft. Therefore, development of prognostics solutions for electronics is of key importance. This paper presents an accelerated aging system for gate-controlled power transistors. This system allows for the understanding of the effects of failure mechanisms, and the identification of leading indicators of failure which are essential in the development of physics-based degradation models and RUL prediction. In particular, this system isolates electrical overstress from thermal overstress. Also, this system allows for a precise control of internal temperatures, enabling the exploration of intrinsic failure mechanisms not related to the device packaging. By controlling the temperature within safe operation levels of the device, accelerated aging is induced by electrical overstress only, avoiding the generation of thermal cycles. The temperature is controlled by active thermal-electric units. Several electrical and thermal signals are measured in-situ and recorded for further analysis in the identification of leading indicators of failures. This system, therefore, provides a unique capability in the exploration of different failure mechanisms and the identification of precursors of failure that can be used to provide a health management solution for electronic devices.
Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These Include radiation, extreme temperatures, thermal cycling, to name a few. Preliminary data obtained on new Gallium Nitride and Silicon Carbide power devices under exposure to radiation followed by long term thermal cycling are presented. This work was done in collaboration with GSFC and JPL in support of the NASA Electronic Parts and Packaging (NEPP) Program
No abstract available
No abstract available
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Schottky barrier-type GaAs baseline devices (semiconductor surface etched and then immediately metalized) and GaAs conducting metal oxide-semiconductor devices are fabricated and characterized. The baseline surfaces (no purposeful oxide) are prepared by a basic or an acidic etch, while the surface for the MIS devices are prepared by oxidizing after the etch step. The metallizations used are thin-film Au, Ag, Pd, and Al. It is shown that the introduction of purposeful oxide into these Schottky barrier-type structures examined on n-type GaAs modifies the barrier formation, and that thin interfacial layers can modify barrier formation through trapping and perhaps chemical reactions. For Au- and Pd-devices, enhanced photovoltaic performance of the MIS configuration is due to increased barrier height.
Report evaluates effects of power and temperature overstress on Motorola and National Semiconductor devices. National Semiconductor devices exceeded 50 percent failure after 160 hours at 225 deg C. Motorola suffered more rejects but failures occurred at 300 deg C. Difference in lead bonding technique may explain performance.
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