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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS2007

Wide-Temperature-Range Integrated Operational Amplifier

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Mojarradi, Mohammad↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2010

Method and Circuit for In-Situ Health Monitoring of Solar Cells in Space

This innovation represents a method and circuit realization of a system designed to make in-situ measurements of test solar-cell operational parameters on orbit using readily available high-temperature and high-ionizing-radiation- tolerant electronic components. This innovation enables on-orbit in-situ solar-array health monitoring and is in response to a need recognized by the U.S. Air Force for future solar arrays for unmanned spacecraft. This system can also be constructed out of commercial-grade electronics and can be embedded into terrestrial solar power system as a diagnostics instrument. This innovation represents a novel approach to I-V curve measurement that is radiation and temperature hard, consumes very few system resources, is economical, and utilizes commercially available components. The circuit will also operate at temperatures as low as 55 C and up to +225 C, allowing it to reside close to the array in direct sunlight. It uses a swept mode transistor functioning as a resistive load while utilizing the solar cells themselves as the biasing device, so the size of the instrument is small and there is no danger of over-driving the cells. Further, this innovation utilizes nearly universal spacecraft bus resources and therefore can be readily adapted to any spacecraft bus allowing for ease of retrofit, or designed into new systems without requiring the addition of infrastructure. One unique characteristic of this innovation is that it effects the measurement of I-V curves without the use of large resistor arrays or active current sources normally used to characterize cells. A single transistor is used as a variable resistive load across the cell. This multi-measurement instrument was constructed using operational amplifiers, analog switches, voltage regulators, MOSFETs, resistors, and capacitors. The operational amplifiers, analog switches, and voltage regulators are silicon-on-insulator (SOI) technology known for its hardness to the effects of ionizing radiation. The SOI components used can tolerate temperatures up to 225 C, which gives plenty of thermal headroom allowing this circuit to perhaps reside in the solar cell panel itself where temperatures can reach over 100 C.

Krasowski, Michael J.↗
NASA NTRS2011

Rotation Rate of Saturn's Magnetosphere using CAPS Plasma Measurements

We present the present status of an investigation of the rotation rate of Saturn's magnetosphere using a 3D velocity moment technique being developed at Goddard which is similar to the 2D version used by Sittler et al. for SOI and similar to that used by Thomsen et al.. This technique allows one to nearly cover the full energy range of the Cassini Plasma Spectrometer (CAPS) IMS from 1 V . E/Q < 50 kV. Since our technique maps the observations into a local inertial frame, it does work during roll maneuvers. We make comparisons with the bi-Maxwellian fitting technique developed by Wilson et al. and the similar velocity moment technique by Thomsen et al. . We concentrate our analysis when ion composition data is available, which is used to weight the non-compositional data, referred to as singles data, to separate H+, H2+ and water group ions (W+) from each other. The chosen periods have high enough telemetry rates (4 kbps or higher) so that coincidence ion data, similar to that used by Sittler et al. for SOI is available. The ion data set is especially valuable for measuring flow velocities for protons, which are more difficult to derive using singles data within the inner magnetosphere, where the signal is dominated by heavy ions (i.e., proton peak merges with W+ peak as low energy shoulder). Our technique uses a flux function, which is zero in the proper plasma flow frame, to estimate fluid parameter uncertainties. The comparisons investigate the experimental errors and potential for systematic errors in the analyses, including ours. The rolls provide the best data set when it comes to getting 4PI coverage of the plasma but are more susceptible to time aliasing effects. In the future we will then make comparisons with magnetic field observations, Saturn ionosphere conductivities as presently known and the field aligned currents necessary for the planet to enforce corotation of the rotating plasma.

Sittler, E.↗
NASA NTRS2016

500 C Electronic Packaging and Dielectric Materials for High Temperature Applications

High-temperature environment operable sensors and electronics are required for exploring the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and application of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high temperature electronics, and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by these high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed. High-temperature environment operable sensors and electronics are required for probing the inner solar planets and distributed control of next generation aeronautical engines. Various silicon carbide (SiC) high temperature sensors, actuators, and electronics have been demonstrated at and above 500C. A compatible packaging system is essential for long-term testing and eventual applications of high temperature electronics and sensors. High temperature passive components are also necessary for high temperature electronic systems. This talk will discuss ceramic packaging systems developed for high electronics and related testing results of SiC circuits at 500C and silicon-on-insulator (SOI) integrated circuits at temperatures beyond commercial limit facilitated by high temperature packaging technologies. Dielectric materials for high temperature multilayers capacitors will also be discussed.

dielectric performance↗
NASA NTRS2003

Single-event upset in evolving commercial silicon-on-insulator microprocessor technologies

Single-event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes and core voltages. Multiple-bit upsets (MBU) in registers and were measured and compared with single-bit upsets. Also, the scaling of the cross section with reduction of feature size for SOI microprocessors was discussed.

Yoder, G. I.↗
NASA NTRS2024

The Plasma Proton Environment within Saturn’s F-G Ring Gap as Observed by the Cassini Plasma Spectrometer Ion Mass Spectrometer during Saturn Orbit Insertion

We report on the detection of protons and the potential detection of H 2 + between Saturn's F and G rings based on Cassini Plasma Spectrometer (CAPS) Ion Mass Spectrometer (IMS) time-of-flight (TOF) composition measurements acquired during Saturn Orbit Insertion (SOI) outbound pass. The range in dipole L shell is 2.3 < L < 2.8. Initial results based on TOF data were presented in E. C. Sittler et al., 2017. Here we present the latest results of our analysis. During the SOI outbound pass between the F and G rings the CAPS IMS was in a mode of reduced post-acceleration voltage at -6 kV instead of the usual -14.6 kV. This reduced voltage still allows the analysis of protons since 6 keV protons are minimally scattered by the instrument’s ultrathin carbon foils when compared to heavier ions O + and O 2 + , scattering. Background noise from penetrating radiation and ghost peaks produced by foil-scattered O + ions within the instrument were considered in our analysis. The analysis allowed determination of the proton density, temperature and flow velocity, accounting for spacecraft potential by assuming a convected Maxwellian for the proton velocity distribution function. We find average proton density n P = 3.2 ± 1.1 #/cm 3 , proton temperature T P = 1.74 ± 0.12 eV, proton rotational flow speed V P = 24 ± 1.5 km/s and spacecraft potential  SC = -0.8 ±1.5 V. These results are compared with previous theoretical estimates of H + and H 2 + ions within Saturn’s inner magnetosphere.

E C Sittler↗
NASA NTRS2005

Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

bolometer↗
DOE OSTI2025

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗
DOE OSTI2026

Catapult-ASIC-dev

This branch extends the wa-hls4ml (FERMILAB-CODE-2026-09-CSAID) work to ASIC technology nodes (Nangate 45 nm and GlobalFoundries 22FDX FD-SOI) using Siemens Catapult HLS. Code is available at: https://github.com/fastmachinelearning/wa-hls4ml-paper/tree/Catapult-ASIC-dev

Di Guglielmo, Giuseppe [Fermi National Accelerator↗
DOE OSTI2024

Development of prechamber enabled mixing-controlled combustion strategy for ultra-low methane emissions from lean burn natural gas engines

This numerical study explores the optimization of Prechamber Enabled Mixing-Controlled Combustion (PC-MCC) using natural gas in heavy-duty engines, aiming to enhance combustion efficiency to minimize methane slip and NOx emissions. The approach involves a prechamber ignition system, distinct from conventional spark ignition (SI) systems, to initiate combustion of direct injected natural gas. By leveraging the robust ignition characteristics of the prechamber, the PC-MCC method demonstrates significant potential in achieving efficient combustion akin to diesel engines but with lower greenhouse gas emissions. The research evaluates the effects of various geometric and operational parameters on the combustion process and emissions, including prechamber volume, nozzle diameter, direct injector (DI) geometry, and engine operating strategies. Computational Fluid Dynamics (CFD) simulations are utilized, focusing on a heavy-duty, single-cylinder engine modeled after the Caterpillar C9.3B engine. Key findings indicate that a prechamber volume of 3 cc, coupled with a nozzle diameter of 2.75 mm for two prechamber holes, strikes an optimal balance between combustion efficiency and emissions reduction. This configuration ensures robust combustion across a range of operating conditions while maintaining methane slip within targeted limits. Further investigation into DI geometry shows the significance of the injector umbrella angle and nozzle diameter in shaping the fuel-air mixing and combustion dynamics. An umbrella angle of 130° and a nozzle diameter of 300 microns are identified as optimal, promoting rapid and efficient combustion with minimized methane and NOx emissions. The study also investigates the impact of injection timing and pressure, highlighting their roles in controlling combustion timing and influencing emissions levels. Advanced injection timing is found to be crucial in achieving the desired low methane slip, whereas retarded injection timing assists to reduce NOx emissions while having a slight increase in methane emissions. Operating strategies incorporating various levels of Exhaust Gas Recirculation (EGR) are assessed for their effectiveness in further reducing emissions. The research demonstrates that a judicious combination of internal hot EGR and careful calibration of DI pressure and SOI timing can achieve significant reductions in NOx emissions while keeping methane slip under control. Specifically, an internal EGR level of 15%–25%, combined with DI pressures of 200–300 bar and injection timings at or after top dead center, is recommended. These findings contribute valuable insights into the development of advanced combustion techniques for natural gas engines, offering a viable pathway to reduce methane slip without compromising engine efficiency or performance. The PC-MCC system presents a promising solution for the future of heavy-duty natural gas engine technology to reduce methane emissions.

Nsaif, Osama↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2025

An Architectural Survey of the U12G Tunnel Historic District, Nevada National Security Site, Nye County, Nevada

The U.S. Department of Energy (DOE), in conjunction with the National Nuclear Security Administration Nevada Field Office (NNSA/NFO), proposes to demolish six buildings and three storage areas located at the U12g Tunnel portal area in Area 12 of the Nevada National Security Site (NNSS). The buildings are 12-358 (Signal Vault); 12-201800 (Storage Quonset Hut); 12-202555 (Walker Shack); 12-868 (Pipe Assembly); 12-B100933 (Electrical Shop); 12-B100944 (Conference Room); and Storage Area 1; Storage Area 2; and Storage Area 3. The buildings and storage areas were selected for demolition as part of the DOE’s Real Property Efficiency Plan to reduce the footprint of unused and non-operational facilities on the NNSS. They are all vacant and have no proposed uses for current or upcoming NNSS missions. Demolition activities constitute an undertaking subject to review under Section 106 of the National Historic Preservation Act (NHPA) (54 United States Code [USC] § 306101) and its implementing regulations, 36 Code of Federal Regulations (CFR) Part 800. Identification efforts began with resources proposed for demolition in federal Fiscal Year (FY) 23. Four buildings were proposed to be demolished in FY23 (12-358, 12-868, 12-201800, and 12-202555). These buildings and the U12g Tunnel Historic District (SHPO No. D444) were recorded in Identification, Evaluation, and Finding of Adverse Effect for the Proposed Demolition of Five Buildings in Area 12, Nevada National Security Site, Nye County, Nevada (Menocal et al. 2023). Identification efforts indicated three buildings (12-358, 12-201800, and 12-868) supported nuclear testing in the U12g Tunnel. The fourth building post-dated the use of U12g Tunnel for nuclear testing activities. The report recommended that three of the four buildings (12-358, 12-201800, 12-868) and the U12g Tunnel Historic District may be eligible for the National Register of Historic Places (NRHP). The report also found that the undertaking would have an adverse effect on the three buildings and on the historic district. The Nevada State Historic Preservation Office (SHPO) concurred with the report’s findings (Reed 2023). The U12g Tunnel was determined eligible as a historic district under the Secretary of the Interior’s (SOI) Significance Criterion A, at the local level, in the context of the Cold War as an underground testing environment for the development of nuclear weapons and to assess the effects of a nuclear explosion on materials and equipment with a period of significance from 1959 to 1971. It was also determined eligible under Significance Criterion C for embodying the distinctive characters of a horizontal tunnel complex used for nuclear testing and as a significant and distinguishable entity. The three buildings were determined to be contributing elements of the district. The undertaking was expanded with the addition of two buildings and three storage areas proposed to be demolished and located within U12g Tunnel Historic District in FY24. These five resources (12-B100933, 12-B100944, and Storage Areas 1, 2, and 3) were recorded in Supplemental Identification, Evaluation, and Finding of Effect for Additional Proposed Demolition at U12g Tunnel, Area 12, Nevada national Security Site, Nye County, Nevada (Brannan et al. 2024). Identification efforts indicated that the two buildings and Storage Area 1 supported nuclear testing in the U12g Tunnel. Storage Area 1 and Storage Area 2 post-dated the nuclear testing activities at U12g Tunnel and were not recommended as contributing elements to the district. The report also found that the undertaking would have an adverse effect on the newly identified buildings and one storage area and on the historic district. The SHPO concurred that the expanded undertaking would result in adverse effects to historic properties (Reed 2025). To resolve these adverse effects, NNSA/NFO, in consultation with the SHPO, is following standard mitigation as stipulated in the 2024 Programmatic Agreement DE-GM58-22NA25554 Among the U.S. Department of Energy and the Nevada State Historic Preservation Officer and the Advisory Council on Historic Preservation Concerning the Protection of Historic Properties on the Nevada National Security Site, Nye County, Nevada (hereafter referred to as the NNSS PA). The standard mitigation measures are outlined in Appendix D of the NNSS PA. As such, this architectural survey has been prepared in accordance with Appendix D of the NNSS PA and follows the report format outlined in Appendix F. It includes a historic context that describes the district’s origin, history, and support functions, its significance in the context of nuclear testing on the NNSS, and identifies contributing and non-contributing elements within the district. The report is accompanied by Architectural Resource Assessment (ARA) forms for individual resources and a Historic District Resource Assessment (HDRA) for the U12g Tunnel Historic District. In total, this architectural report identified 32 primary resources within the district boundary. Six of the primary resources were previously identified as contributing elements. An additional 17 resources are recommended as contributing elements to the district for a total of 23 contributing elements. The other nine resources identified are recommended as non-contributing elements to the district.

12-201800↗