Development of MNOS technology Final report
Metal nitride oxide semiconductor structures for amplifying and memory
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Improvement of Screening Methods for Silicon Planar Devices Quarterly Progress Report, 1 Apr. - 30 Jun. 1970
Screening measurements and fabrication of metal oxide semiconductor and multilayer-bipolar wafers
Berger, W. M.↗
Complementary MOS and bipolar make it together on a single chip
Complementary metal oxide semiconductor and bipolar transistors fabrication on same integrated circuit chip by C-squared technology
Cook, R.↗
Polarographic carbon dioxide transducer amplifier
Electronic amplifier contains matched pair of metal oxide semiconductor field effect transistor devices which have high input impedance and long-term stability. Thermistor in feedback loop provides temperature compensation for large drifts in the sensor.
Stillman, G.↗
Establishing an electrical test philosophy for LSI microcircuits, volume 1 Final report, 15 May 1970 - 15 Feb. 1971
Large scale integration and metal oxide semiconductor microelectronic testing techniques including combinatorial, sequential, functional, and parametric methods
Keonjian, E.↗
Miniature biotelemeter gives multichannel wideband biomedical data
A miniature biotelemeter was developed for sensing and transmitting multiple channels of biomedical data over a radio link. The design of this miniature, 10-channel, wideband (5 kHz/channel), pulse amplitude modulation/ frequency modulation biotelemeter takes advantage of modern device technology (e.g., integrated circuit operational amplifiers, complementary symmetry/metal oxide semiconductor logic, and solid state switches) and hybrid packaging techniques. The telemeter is being used to monitor 10 channels of neuron firings from specific regions of the brain in rats implanted with chronic electrodes. Design, fabrication, and testing of an engineering model biotelemeter are described.
Carraway, J. B.↗
The NASA computer aided design and test system
A family of computer programs facilitating the design, layout, evaluation, and testing of digital electronic circuitry is described. CADAT (computer aided design and test system) is intended for use by NASA and its contractors and is aimed predominantly at providing cost effective microelectronic subsystems based on custom designed metal oxide semiconductor (MOS) large scale integrated circuits (LSIC's). CADAT software can be easily adopted by installations with a wide variety of computer hardware configurations. Its structure permits ease of update to more powerful component programs and to newly emerging LSIC technologies. The components of the CADAT system are described stressing the interaction of programs rather than detail of coding or algorithms. The CADAT system provides computer aids to derive and document the design intent, includes powerful automatic layout software, permits detailed geometry checks and performance simulation based on mask data, and furnishes test pattern sequences for hardware testing.
Gould, J. M.↗
Design, processing, and testing of LSI arrays for space station
The development of a beam-leaded low power, high performance metal-oxide-semiconductor (MOS), 256-bit random access memory (RAM) was reported. Previous success with the aluminum-gate current-sense version and a silicon-gate voltage-sense version led to the present effort to make a beam-leaded silicon-gate RAM. Some problems unique to the silicon-on-sapphire beam-lead process development are presented. Beam-leaded SOS TA5388 devices using a Si3N4 passivation layer were shown to have good electrical parameters.
Schneider, W. C.↗
Interface control scheme for computer high-speed interface unit
Control scheme is general and performs for multiplexed and dedicated channels as well as for data-bus interfaces. Control comprises two 64-pin, dual in-line packages, each of which holds custom large-scale integrated array built with silicon-on-sapphire complementary metal-oxide semiconductor technology.
Ballard, B. K.↗
Interactive graphical computer-aided design system
System is used for design, layout, and modification of large-scale-integrated (LSI) metal-oxide semiconductor (MOS) arrays. System is structured around small computer which provides real-time support for graphics storage display unit with keyboard, slave display unit, hard copy unit, and graphics tablet for designer/computer interface.
Edge, T. M.↗
CMOS array design automation techniques
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.
Ramondetta, P.↗
LOGSIM programmer's manual
A programmer's manual is reported for a Logic Simulator (LOGSIM) computer program that is a large capacity event simulator with the capability to accurately simulate the effects of certain unknown states, rise and fall times, and floating nodes in large scale metal oxide semiconductor logic circuits. A detailed description of the software with flow charts is included within the report.
Mitchell, C. L.↗
Prediction and measurement of radiation damage to CMOS devices on board spacecraft
The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.
Cliff, R. A.↗
Voltage stress effects on microcircuit accelerated life test failure rates
The applicability of Arrhenius and Eyring reaction rate models for describing microcircuit aging characteristics as a function of junction temperature and applied voltage was evaluated. The results of a matrix of accelerated life tests with a single metal oxide semiconductor microcircuit operated at six different combinations of temperature and voltage were used to evaluate the models. A total of 450 devices from two different lots were tested at ambient temperatures between 200 C and 250 C and applied voltages between 5 Vdc and 15 Vdc. A statistical analysis of the surface related failure data resulted in bimodal failure distributions comprising two lognormal distributions; a 'freak' distribution observed early in time, and a 'main' distribution observed later in time. The Arrhenius model was shown to provide a good description of device aging as a function of temperature at a fixed voltage. The Eyring model also appeared to provide a reasonable description of main distribution device aging as a function of temperature and voltage. Circuit diagrams are shown.
Johnson, G. M.↗
Record dielectric breakdown automatically
Automatic Monitoring System for time-dependent dielectric breakdown tests ninety-nine metal-oxide semiconductor capacitors simultaneously. Each breakdown generates voltage spike registered on readouts and indicated by LED. Latching circuit prevents recording of possible subsequent breakdowns in same capacitor. In addition to research use, system could also be adapted for quality control.
Bates, E. T., Jr.↗
Safe handling practices for electrostatic-sensitive devices
Review is detailed compilation of safe handling practices for Metal-Oxide Semiconductor (MOS) circuit elements and other devices that are susceptible to damage by electrostatic discharge. Article lists safety procedures for all aspects of handling and use of these components. Included are guidelines for setting up static-free work station and list of materials and equipment needed to maintain antistatic protection. Appendix gives vendors of these items.
Herring, L. L.↗
Ion-beam sputtering increases solar-cell efficiency
Ion-beam sputtering, fabrication of oxide-semiconductor-on-silicon (OSOS) solar cells, results in cells of 12% efficiency. Ion-beam sputtering technique is compatible with low-cost continuous fabrication and requires no high-temperature processing.
Burk, D. E.↗
Complementary DMOS/VMOS integrated-circuit-structure
Complementary metal-oxide-semiconductor (CMOS) structure has relatively high speed, high breakdown voltage, high transconductance and high packing densities.
Jhabvala, M. D.↗